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0740a1bead
This helps clean up some of the mess when expanding unaligned 64-bit loads when changed to be promote to v2i32, and fixes situations where or x, 0 was emitted after splitting 64-bit ors during moveToVALU. I think this could be a generic combine but I'm not sure. llvm-svn: 266104
42 lines
1.5 KiB
LLVM
42 lines
1.5 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}zext_or_operand_i64:
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; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
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; GCN: buffer_load_dword v[[LD32:[0-9]+]]
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; GCN-NOT: _or_
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; GCN-NOT: v[[HI]]
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; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; GCN: v_or_b32_e32 v[[LO]], v[[LD32]], v[[LO]]
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; GCN-NOT: _or_
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; GCN-NOT: v[[HI]]
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; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
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define void @zext_or_operand_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i32 addrspace(1)* %in1) {
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%ld.64 = load volatile i64, i64 addrspace(1)* %in0
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%ld.32 = load volatile i32, i32 addrspace(1)* %in1
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%ext = zext i32 %ld.32 to i64
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%or = or i64 %ld.64, %ext
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}zext_or_operand_commute_i64:
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; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
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; GCN: buffer_load_dword v[[LD32:[0-9]+]]
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; GCN-NOT: _or_
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; GCN-NOT: v[[HI]]
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; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; GCN: v_or_b32_e32 v[[LO]], v[[LD32]], v[[LO]]
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; GCN-NOT: v[[HI]]
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; GCN-NOT: _or_
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; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
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define void @zext_or_operand_commute_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i32 addrspace(1)* %in1) {
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%ld.64 = load volatile i64, i64 addrspace(1)* %in0
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%ld.32 = load volatile i32, i32 addrspace(1)* %in1
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%ext = zext i32 %ld.32 to i64
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%or = or i64 %ext, %ld.64
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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