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525 lines
19 KiB
TableGen
525 lines
19 KiB
TableGen
//===- PIC16InstrInfo.td - PIC16 Instruction defs -------------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the PIC16 instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// PIC16 Specific Type Constraints.
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//===----------------------------------------------------------------------===//
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class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
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class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
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//===----------------------------------------------------------------------===//
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// PIC16 Specific Type Profiles.
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//===----------------------------------------------------------------------===//
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// Generic type profiles for i8/i16 unary/binary operations.
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// Taking one i8 or i16 and producing void.
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def SDTI8VoidOp : SDTypeProfile<0, 1, [SDTCisI8<0>]>;
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def SDTI16VoidOp : SDTypeProfile<0, 1, [SDTCisI16<0>]>;
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// Taking one value and producing an output of same type.
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def SDTI8UnaryOp : SDTypeProfile<1, 1, [SDTCisI8<0>, SDTCisI8<1>]>;
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def SDTI16UnaryOp : SDTypeProfile<1, 1, [SDTCisI16<0>, SDTCisI16<1>]>;
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// Taking two values and producing an output of same type.
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def SDTI8BinOp : SDTypeProfile<1, 2, [SDTCisI8<0>, SDTCisI8<1>, SDTCisI8<2>]>;
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def SDTI16BinOp : SDTypeProfile<1, 2, [SDTCisI16<0>, SDTCisI16<1>,
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SDTCisI16<2>]>;
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// Node specific type profiles.
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def SDT_PIC16Load : SDTypeProfile<1, 3, [SDTCisI8<0>, SDTCisI8<1>,
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SDTCisI8<2>, SDTCisI8<3>]>;
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def SDT_PIC16Store : SDTypeProfile<0, 4, [SDTCisI8<0>, SDTCisI8<1>,
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SDTCisI8<2>, SDTCisI8<3>]>;
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def SDT_PIC16Connect : SDTypeProfile<1, 2, [SDTCisI8<0>, SDTCisI8<1>,
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SDTCisI8<2>]>;
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// PIC16ISD::CALL type prorile
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def SDT_PIC16call : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
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def SDT_PIC16callw : SDTypeProfile<1, -1, [SDTCisInt<0>]>;
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// PIC16ISD::BRCOND
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def SDT_PIC16Brcond: SDTypeProfile<0, 2,
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[SDTCisVT<0, OtherVT>, SDTCisI8<1>]>;
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// PIC16ISD::BRCOND
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def SDT_PIC16Selecticc: SDTypeProfile<1, 3,
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[SDTCisI8<0>, SDTCisI8<1>, SDTCisI8<2>,
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SDTCisI8<3>]>;
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//===----------------------------------------------------------------------===//
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// PIC16 addressing modes matching via DAG.
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//===----------------------------------------------------------------------===//
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def diraddr : ComplexPattern<i8, 1, "SelectDirectAddr", [], []>;
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//===----------------------------------------------------------------------===//
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// PIC16 Specific Node Definitions.
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//===----------------------------------------------------------------------===//
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def PIC16callseq_start : SDNode<"ISD::CALLSEQ_START", SDTI8VoidOp,
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[SDNPHasChain, SDNPOutFlag]>;
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def PIC16callseq_end : SDNode<"ISD::CALLSEQ_END", SDTI8VoidOp,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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// Low 8-bits of GlobalAddress.
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def PIC16Lo : SDNode<"PIC16ISD::Lo", SDTI8BinOp>;
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// High 8-bits of GlobalAddress.
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def PIC16Hi : SDNode<"PIC16ISD::Hi", SDTI8BinOp>;
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// The MTHI and MTLO nodes are used only to match them in the incoming
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// DAG for replacement by corresponding set_fsrhi, set_fsrlo insntructions.
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// These nodes are not used for defining any instructions.
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def MTLO : SDNode<"PIC16ISD::MTLO", SDTI8UnaryOp>;
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def MTHI : SDNode<"PIC16ISD::MTHI", SDTI8UnaryOp>;
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def MTPCLATH : SDNode<"PIC16ISD::MTPCLATH", SDTI8UnaryOp>;
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// Node to generate Bank Select for a GlobalAddress.
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def Banksel : SDNode<"PIC16ISD::Banksel", SDTI8UnaryOp>;
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// Node to match a direct store operation.
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def PIC16Store : SDNode<"PIC16ISD::PIC16Store", SDT_PIC16Store, [SDNPHasChain]>;
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def PIC16StWF : SDNode<"PIC16ISD::PIC16StWF", SDT_PIC16Store,
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[SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
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// Node to match a direct load operation.
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def PIC16Load : SDNode<"PIC16ISD::PIC16Load", SDT_PIC16Load, [SDNPHasChain]>;
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def PIC16LdArg : SDNode<"PIC16ISD::PIC16LdArg", SDT_PIC16Load, [SDNPHasChain]>;
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def PIC16LdWF : SDNode<"PIC16ISD::PIC16LdWF", SDT_PIC16Load,
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[SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
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def PIC16Connect: SDNode<"PIC16ISD::PIC16Connect", SDT_PIC16Connect, []>;
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// Node to match PIC16 call
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def PIC16call : SDNode<"PIC16ISD::CALL", SDT_PIC16call,
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[SDNPHasChain , SDNPOptInFlag, SDNPOutFlag]>;
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def PIC16callw : SDNode<"PIC16ISD::CALLW", SDT_PIC16callw,
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[SDNPHasChain , SDNPOptInFlag, SDNPOutFlag]>;
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// Node to match a comparison instruction.
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def PIC16Subcc : SDNode<"PIC16ISD::SUBCC", SDTI8BinOp, [SDNPOutFlag]>;
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// Node to match a conditional branch.
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def PIC16Brcond : SDNode<"PIC16ISD::BRCOND", SDT_PIC16Brcond,
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[SDNPHasChain, SDNPInFlag]>;
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def PIC16Selecticc : SDNode<"PIC16ISD::SELECT_ICC", SDT_PIC16Selecticc,
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[SDNPInFlag]>;
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//===----------------------------------------------------------------------===//
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// PIC16 Operand Definitions.
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//===----------------------------------------------------------------------===//
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def i8mem : Operand<i8>;
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def brtarget: Operand<OtherVT>;
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// Operand for printing out a condition code.
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let PrintMethod = "printCCOperand" in
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def CCOp : Operand<i8>;
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include "PIC16InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// PIC16 Common Classes.
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//===----------------------------------------------------------------------===//
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// W = W Op F : Load the value from F and do Op to W.
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let isTwoAddress = 1, mayLoad = 1 in
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class BinOpFW<bits<6> OpCode, string OpcStr, SDNode OpNode>:
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ByteFormat<OpCode, (outs GPR:$dst),
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(ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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!strconcat(OpcStr, " $ptrlo + $offset, W"),
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[(set GPR:$dst, (OpNode GPR:$src, (PIC16Load diraddr:$ptrlo,
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(i8 imm:$ptrhi),
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(i8 imm:$offset))))]>;
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// F = F Op W : Load the value from F, do op with W and store in F.
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// This insn class is not marked as TwoAddress because the reg is
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// being used as a source operand only. (Remember a TwoAddress insn
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// needs a copyRegToReg.)
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let mayStore = 1 in
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class BinOpWF<bits<6> OpCode, string OpcStr, SDNode OpNode>:
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ByteFormat<OpCode, (outs),
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(ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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!strconcat(OpcStr, " $ptrlo + $offset"),
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[(PIC16Store (OpNode GPR:$src, (PIC16Load diraddr:$ptrlo,
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(i8 imm:$ptrhi),
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(i8 imm:$offset))),
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diraddr:$ptrlo,
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(i8 imm:$ptrhi), (i8 imm:$offset)
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)]>;
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// W = W Op L : Do Op of L with W and place result in W.
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let isTwoAddress = 1 in
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class BinOpLW<bits<6> opcode, string OpcStr, SDNode OpNode> :
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LiteralFormat<opcode, (outs GPR:$dst),
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(ins GPR:$src, i8imm:$literal),
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!strconcat(OpcStr, " $literal"),
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[(set GPR:$dst, (OpNode GPR:$src, (i8 imm:$literal)))]>;
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//===----------------------------------------------------------------------===//
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// PIC16 Instructions.
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions.
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def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i8imm:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(PIC16callseq_start imm:$amt)]>;
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def ADJCALLSTACKUP : Pseudo<(outs), (ins i8imm:$amt),
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"!ADJCALLSTACKUP $amt",
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[(PIC16callseq_end imm:$amt)]>;
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//-----------------------------------
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// Vaious movlw insn patterns.
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//-----------------------------------
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let isReMaterializable = 1 in {
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// Move 8-bit literal to W.
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def movlw : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src),
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"movlw $src",
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[(set GPR:$dst, (i8 imm:$src))]>;
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// Move a Lo(TGA) to W.
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def movlw_lo_1 : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src, i8imm:$src2),
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"movlw LOW(${src} + ${src2})",
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[(set GPR:$dst, (PIC16Lo tglobaladdr:$src, imm:$src2 ))]>;
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// Move a Lo(TES) to W.
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def movlw_lo_2 : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src, i8imm:$src2),
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"movlw LOW(${src} + ${src2})",
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[(set GPR:$dst, (PIC16Lo texternalsym:$src, imm:$src2 ))]>;
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// Move a Hi(TGA) to W.
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def movlw_hi_1 : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src, i8imm:$src2),
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"movlw HIGH(${src} + ${src2})",
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[(set GPR:$dst, (PIC16Hi tglobaladdr:$src, imm:$src2))]>;
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// Move a Hi(TES) to W.
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def movlw_hi_2 : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src, i8imm:$src2),
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"movlw HIGH(${src} + ${src2})",
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[(set GPR:$dst, (PIC16Hi texternalsym:$src, imm:$src2))]>;
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}
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//-------------------
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// FSR setting insns.
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//-------------------
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// These insns are matched via a DAG replacement pattern.
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def set_fsrlo:
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ByteFormat<0, (outs FSR16:$fsr),
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(ins GPR:$val),
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"movwf ${fsr}L",
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[]>;
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let isTwoAddress = 1 in
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def set_fsrhi:
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ByteFormat<0, (outs FSR16:$dst),
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(ins FSR16:$src, GPR:$val),
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"movwf ${dst}H",
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[]>;
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def set_pclath:
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ByteFormat<0, (outs PCLATHR:$dst),
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(ins GPR:$val),
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"movwf ${dst}",
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[(set PCLATHR:$dst , (MTPCLATH GPR:$val))]>;
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//----------------------------
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// copyRegToReg
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// copyRegToReg insns. These are dummy. They should always be deleted
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// by the optimizer and never be present in the final generated code.
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// if they are, then we have to write correct macros for these insns.
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//----------------------------
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def copy_fsr:
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Pseudo<(outs FSR16:$dst), (ins FSR16:$src), "copy_fsr $dst, $src", []>;
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def copy_w:
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Pseudo<(outs GPR:$dst), (ins GPR:$src), "copy_w $dst, $src", []>;
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class SAVE_FSR<string OpcStr>:
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Pseudo<(outs),
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(ins FSR16:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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!strconcat(OpcStr, " $ptrlo, $offset"),
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[]>;
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def save_fsr0: SAVE_FSR<"save_fsr0">;
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def save_fsr1: SAVE_FSR<"save_fsr1">;
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class RESTORE_FSR<string OpcStr>:
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Pseudo<(outs FSR16:$dst),
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(ins i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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!strconcat(OpcStr, " $ptrlo, $offset"),
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[]>;
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def restore_fsr0: RESTORE_FSR<"restore_fsr0">;
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def restore_fsr1: RESTORE_FSR<"restore_fsr1">;
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//--------------------------
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// Store to memory
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//-------------------------
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// Direct store.
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// Input operands are: val = W, ptrlo = GA, offset = offset, ptrhi = banksel.
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let mayStore = 1 in
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class MOVWF_INSN<bits<6> OpCode, SDNode OpNodeDest, SDNode Op>:
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ByteFormat<0, (outs),
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(ins GPR:$val, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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"movwf ${ptrlo} + ${offset}",
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[(Op GPR:$val, OpNodeDest:$ptrlo, (i8 imm:$ptrhi),
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(i8 imm:$offset))]>;
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// Store W to a Global Address.
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def movwf : MOVWF_INSN<0, tglobaladdr, PIC16Store>;
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// Store W to an External Symobol.
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def movwf_1 : MOVWF_INSN<0, texternalsym, PIC16Store>;
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// Store with InFlag and OutFlag
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// This is same as movwf_1 but has a flag. A flag is required to
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// order the stores while passing the params to function.
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def movwf_2 : MOVWF_INSN<0, texternalsym, PIC16StWF>;
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// Indirect store. Matched via a DAG replacement pattern.
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def store_indirect :
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ByteFormat<0, (outs),
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(ins GPR:$val, FSR16:$fsr, i8imm:$offset),
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"movwi $offset[$fsr]",
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[]>;
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//----------------------------
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// Load from memory
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//----------------------------
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// Direct load.
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// Input Operands are: ptrlo = GA, offset = offset, ptrhi = banksel.
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// Output: dst = W
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let Defs = [STATUS], mayLoad = 1 in
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class MOVF_INSN<bits<6> OpCode, SDNode OpNodeSrc, SDNode Op>:
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ByteFormat<0, (outs GPR:$dst),
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(ins i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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"movf ${ptrlo} + ${offset}, W",
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[(set GPR:$dst,
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(Op OpNodeSrc:$ptrlo, (i8 imm:$ptrhi),
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(i8 imm:$offset)))]>;
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// Load from a GA.
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def movf : MOVF_INSN<0, tglobaladdr, PIC16Load>;
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// Load from an ES.
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def movf_1 : MOVF_INSN<0, texternalsym, PIC16Load>;
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def movf_1_1 : MOVF_INSN<0, texternalsym, PIC16LdArg>;
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// Load with InFlag and OutFlag
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// This is same as movf_1 but has a flag. A flag is required to
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// order the loads while copying the return value of a function.
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def movf_2 : MOVF_INSN<0, texternalsym, PIC16LdWF>;
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// Indirect load. Matched via a DAG replacement pattern.
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def load_indirect :
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ByteFormat<0, (outs GPR:$dst),
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(ins FSR16:$fsr, i8imm:$offset),
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"moviw $offset[$fsr]",
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[]>;
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//-------------------------
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// Bitwise operations patterns
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//--------------------------
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// W = W op [F]
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let Defs = [STATUS] in {
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def OrFW : BinOpFW<0, "iorwf", or>;
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def XOrFW : BinOpFW<0, "xorwf", xor>;
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def AndFW : BinOpFW<0, "andwf", and>;
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// F = W op [F]
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def OrWF : BinOpWF<0, "iorwf", or>;
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def XOrWF : BinOpWF<0, "xorwf", xor>;
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def AndWF : BinOpWF<0, "andwf", and>;
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//-------------------------
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// Various add/sub patterns.
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//-------------------------
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// W = W + [F]
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def addfw_1: BinOpFW<0, "addwf", add>;
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def addfw_2: BinOpFW<0, "addwf", addc>;
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let Uses = [STATUS] in
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def addfwc: BinOpFW<0, "addwfc", adde>; // With Carry.
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// F = W + [F]
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def addwf_1: BinOpWF<0, "addwf", add>;
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def addwf_2: BinOpWF<0, "addwf", addc>;
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let Uses = [STATUS] in
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def addwfc: BinOpWF<0, "addwfc", adde>; // With Carry.
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}
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// W -= [F] ; load from F and sub the value from W.
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let isTwoAddress = 1, mayLoad = 1 in
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class SUBFW<bits<6> OpCode, string OpcStr, SDNode OpNode>:
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ByteFormat<OpCode, (outs GPR:$dst),
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(ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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!strconcat(OpcStr, " $ptrlo + $offset, W"),
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[(set GPR:$dst, (OpNode (PIC16Load diraddr:$ptrlo,
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(i8 imm:$ptrhi), (i8 imm:$offset)),
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GPR:$src))]>;
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let Defs = [STATUS] in {
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def subfw_1: SUBFW<0, "subwf", sub>;
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def subfw_2: SUBFW<0, "subwf", subc>;
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let Uses = [STATUS] in
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def subfwb: SUBFW<0, "subwfb", sube>; // With Borrow.
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}
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let Defs = [STATUS], isTerminator = 1 in
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def subfw_cc: SUBFW<0, "subwf", PIC16Subcc>;
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// [F] -= W ;
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let mayStore = 1 in
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class SUBWF<bits<6> OpCode, string OpcStr, SDNode OpNode>:
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ByteFormat<OpCode, (outs),
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(ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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!strconcat(OpcStr, " $ptrlo + $offset"),
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[(PIC16Store (OpNode (PIC16Load diraddr:$ptrlo,
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(i8 imm:$ptrhi), (i8 imm:$offset)),
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GPR:$src), diraddr:$ptrlo,
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(i8 imm:$ptrhi), (i8 imm:$offset))]>;
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let Defs = [STATUS] in {
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def subwf_1: SUBWF<0, "subwf", sub>;
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def subwf_2: SUBWF<0, "subwf", subc>;
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let Uses = [STATUS] in
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def subwfb: SUBWF<0, "subwfb", sube>; // With Borrow.
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def subwf_cc: SUBWF<0, "subwf", PIC16Subcc>;
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}
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// addlw
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let Defs = [STATUS] in {
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def addlw_1 : BinOpLW<0, "addlw", add>;
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def addlw_2 : BinOpLW<0, "addlw", addc>;
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let Uses = [STATUS] in
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def addlwc : BinOpLW<0, "addlwc", adde>; // With Carry. (Assembler macro).
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// bitwise operations involving a literal and w.
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def andlw : BinOpLW<0, "andlw", and>;
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def xorlw : BinOpLW<0, "xorlw", xor>;
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def orlw : BinOpLW<0, "iorlw", or>;
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}
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// sublw
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// W = C - W ; sub W from literal. (Without borrow).
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|
let isTwoAddress = 1 in
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|
class SUBLW<bits<6> opcode, SDNode OpNode> :
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|
LiteralFormat<opcode, (outs GPR:$dst),
|
|
(ins GPR:$src, i8imm:$literal),
|
|
"sublw $literal",
|
|
[(set GPR:$dst, (OpNode (i8 imm:$literal), GPR:$src))]>;
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|
|
|
let Defs = [STATUS] in {
|
|
def sublw_1 : SUBLW<0, sub>;
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|
def sublw_2 : SUBLW<0, subc>;
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|
}
|
|
let Defs = [STATUS], isTerminator = 1 in
|
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def sublw_cc : SUBLW<0, PIC16Subcc>;
|
|
|
|
// Call instruction.
|
|
let isCall = 1,
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|
Defs = [W, FSR0, FSR1] in {
|
|
def CALL: LiteralFormat<0x1, (outs), (ins i8imm:$func),
|
|
//"call ${func} + 2",
|
|
"call ${func}",
|
|
[(PIC16call diraddr:$func)]>;
|
|
}
|
|
|
|
let isCall = 1,
|
|
Defs = [W, FSR0, FSR1] in {
|
|
def CALL_1: LiteralFormat<0x1, (outs), (ins GPR:$func, PCLATHR:$pc),
|
|
"callw",
|
|
[(PIC16call (PIC16Connect GPR:$func, PCLATHR:$pc))]>;
|
|
}
|
|
|
|
let isCall = 1,
|
|
Defs = [FSR0, FSR1] in {
|
|
def CALLW: LiteralFormat<0x1, (outs GPR:$dest),
|
|
(ins GPR:$func, PCLATHR:$pc),
|
|
"callw",
|
|
[(set GPR:$dest, (PIC16callw (PIC16Connect GPR:$func, PCLATHR:$pc)))]>;
|
|
}
|
|
|
|
let Uses = [STATUS], isBranch = 1, isTerminator = 1, hasDelaySlot = 0 in
|
|
def pic16brcond: ControlFormat<0x0, (outs), (ins brtarget:$dst, CCOp:$cc),
|
|
"b$cc $dst",
|
|
[(PIC16Brcond bb:$dst, imm:$cc)]>;
|
|
|
|
// Unconditional branch.
|
|
let isBranch = 1, isTerminator = 1, hasDelaySlot = 0 in
|
|
def br_uncond: ControlFormat<0x0, (outs), (ins brtarget:$dst),
|
|
"goto $dst",
|
|
[(br bb:$dst)]>;
|
|
|
|
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
|
|
// scheduler into a branch sequence.
|
|
let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
|
|
def SELECT_CC_Int_ICC
|
|
: Pseudo<(outs GPR:$dst), (ins GPR:$T, GPR:$F, i8imm:$Cond),
|
|
"; SELECT_CC_Int_ICC PSEUDO!",
|
|
[(set GPR:$dst, (PIC16Selecticc GPR:$T, GPR:$F,
|
|
imm:$Cond))]>;
|
|
}
|
|
|
|
|
|
// Banksel.
|
|
def banksel :
|
|
Pseudo<(outs),
|
|
(ins i8mem:$ptr),
|
|
"banksel $ptr",
|
|
[]>;
|
|
|
|
def pagesel :
|
|
Pseudo<(outs),
|
|
(ins i8mem:$ptr),
|
|
"movlp $ptr",
|
|
[]>;
|
|
|
|
|
|
// Return insn.
|
|
def Return :
|
|
ControlFormat<0, (outs), (ins), "return", [(ret)]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// PIC16 Replacment Patterns.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Identify an indirect store and select insns for it.
|
|
def : Pat<(PIC16Store GPR:$val, (MTLO GPR:$loaddr), (MTHI GPR:$hiaddr),
|
|
imm:$offset),
|
|
(store_indirect GPR:$val,
|
|
(set_fsrhi (set_fsrlo GPR:$loaddr), GPR:$hiaddr),
|
|
imm:$offset)>;
|
|
|
|
def : Pat<(PIC16StWF GPR:$val, (MTLO GPR:$loaddr), (MTHI GPR:$hiaddr),
|
|
imm:$offset),
|
|
(store_indirect GPR:$val,
|
|
(set_fsrhi (set_fsrlo GPR:$loaddr), GPR:$hiaddr),
|
|
imm:$offset)>;
|
|
|
|
// Identify an indirect load and select insns for it.
|
|
def : Pat<(PIC16Load (MTLO GPR:$loaddr), (MTHI GPR:$hiaddr),
|
|
imm:$offset),
|
|
(load_indirect (set_fsrhi (set_fsrlo GPR:$loaddr), GPR:$hiaddr),
|
|
imm:$offset)>;
|
|
|
|
def : Pat<(PIC16LdWF (MTLO GPR:$loaddr), (MTHI GPR:$hiaddr),
|
|
imm:$offset),
|
|
(load_indirect (set_fsrhi (set_fsrlo GPR:$loaddr), GPR:$hiaddr),
|
|
imm:$offset)>;
|
|
|