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12a71b7b2e
Summary: This change renames the Backend and BackendPrinter to Pipeline and PipelinePrinter respectively. Variables and comments have also been updated to reflect this change. The reason for this rename, is to be slightly more correct about what MCA is modeling. MCA models a Pipeline, which implies some logical sequence of stages. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb, courbet Subscribers: mgorny, javed.absar, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D48496 llvm-svn: 335496
80 lines
2.9 KiB
C++
80 lines
2.9 KiB
C++
//===--------------------- Support.cpp --------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file implements a few helper functions used by various pipeline
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/// components.
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///
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//===----------------------------------------------------------------------===//
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#include "Support.h"
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#include "llvm/MC/MCSchedule.h"
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namespace mca {
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using namespace llvm;
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void computeProcResourceMasks(const MCSchedModel &SM,
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SmallVectorImpl<uint64_t> &Masks) {
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unsigned ProcResourceID = 0;
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// Create a unique bitmask for every processor resource unit.
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// Skip resource at index 0, since it always references 'InvalidUnit'.
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Masks.resize(SM.getNumProcResourceKinds());
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for (unsigned I = 1, E = SM.getNumProcResourceKinds(); I < E; ++I) {
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const MCProcResourceDesc &Desc = *SM.getProcResource(I);
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if (Desc.SubUnitsIdxBegin)
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continue;
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Masks[I] = 1ULL << ProcResourceID;
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ProcResourceID++;
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}
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// Create a unique bitmask for every processor resource group.
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for (unsigned I = 1, E = SM.getNumProcResourceKinds(); I < E; ++I) {
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const MCProcResourceDesc &Desc = *SM.getProcResource(I);
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if (!Desc.SubUnitsIdxBegin)
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continue;
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Masks[I] = 1ULL << ProcResourceID;
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for (unsigned U = 0; U < Desc.NumUnits; ++U) {
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uint64_t OtherMask = Masks[Desc.SubUnitsIdxBegin[U]];
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Masks[I] |= OtherMask;
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}
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ProcResourceID++;
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}
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}
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double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
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unsigned NumMicroOps,
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ArrayRef<unsigned> ProcResourceUsage) {
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// The block throughput is bounded from above by the hardware dispatch
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// throughput. That is because the DispatchWidth is an upper bound on the
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// number of opcodes that can be part of a single dispatch group.
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double Max = static_cast<double>(NumMicroOps) / DispatchWidth;
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// The block throughput is also limited by the amount of hardware parallelism.
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// The number of available resource units affects the resource pressure
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// distribution, as well as how many blocks can be executed every cycle.
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for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
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unsigned ResourceCycles = ProcResourceUsage[I];
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if (!ResourceCycles)
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continue;
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const MCProcResourceDesc &MCDesc = *SM.getProcResource(I);
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double Throughput = static_cast<double>(ResourceCycles) / MCDesc.NumUnits;
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Max = std::max(Max, Throughput);
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}
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// The block reciprocal throughput is computed as the MAX of:
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// - (NumMicroOps / DispatchWidth)
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// - (NumUnits / ResourceCycles) for every consumed processor resource.
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return Max;
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}
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} // namespace mca
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