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9dc3cc7593
PR36061 showed that during the expansion of ISD::FPOWI, that there was an incorrect zero extension of the integer argument which for MIPS64 would then give incorrect results. Address this with the existing mechanism for correcting sign extensions. This resolves PR36061. Thanks to James Cowgill for reporting the issue! Reviewers: atanasyan, hfinkel Differential Revision: https://reviews.llvm.org/D42537 llvm-svn: 323781
66 lines
2.3 KiB
LLVM
66 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -target-abi n64 | FileCheck %s --check-prefix=MIPSN64
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; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -target-abi n32 | FileCheck %s --check-prefix=MIPSN32
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; Test that powi has its integer argument sign extended on mips64.
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declare double @llvm.powi.f64(double, i32)
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define double @powi(double %value, i32 %power) {
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; MIPSN64-LABEL: powi:
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; MIPSN64: # %bb.0:
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; MIPSN64-NEXT: daddiu $sp, $sp, -16
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; MIPSN64-NEXT: .cfi_def_cfa_offset 16
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; MIPSN64-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
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; MIPSN64-NEXT: .cfi_offset 31, -8
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; MIPSN64-NEXT: jal __powidf2
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; MIPSN64-NEXT: sll $5, $5, 0
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; MIPSN64-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
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; MIPSN64-NEXT: jr $ra
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; MIPSN64-NEXT: daddiu $sp, $sp, 16
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;
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; MIPSN32-LABEL: powi:
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; MIPSN32: # %bb.0:
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; MIPSN32-NEXT: addiu $sp, $sp, -16
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; MIPSN32-NEXT: .cfi_def_cfa_offset 16
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; MIPSN32-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
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; MIPSN32-NEXT: .cfi_offset 31, -8
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; MIPSN32-NEXT: jal __powidf2
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; MIPSN32-NEXT: sll $5, $5, 0
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; MIPSN32-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
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; MIPSN32-NEXT: jr $ra
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; MIPSN32-NEXT: addiu $sp, $sp, 16
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%1 = tail call double @llvm.powi.f64(double %value, i32 %power)
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ret double %1
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}
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declare float @llvm.powi.f32(float, i32)
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define float @powfi(float %value, i32 %power) {
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; MIPSN64-LABEL: powfi:
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; MIPSN64: # %bb.0:
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; MIPSN64-NEXT: daddiu $sp, $sp, -16
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; MIPSN64-NEXT: .cfi_def_cfa_offset 16
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; MIPSN64-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
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; MIPSN64-NEXT: .cfi_offset 31, -8
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; MIPSN64-NEXT: jal __powisf2
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; MIPSN64-NEXT: sll $5, $5, 0
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; MIPSN64-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
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; MIPSN64-NEXT: jr $ra
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; MIPSN64-NEXT: daddiu $sp, $sp, 16
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;
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; MIPSN32-LABEL: powfi:
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; MIPSN32: # %bb.0:
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; MIPSN32-NEXT: addiu $sp, $sp, -16
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; MIPSN32-NEXT: .cfi_def_cfa_offset 16
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; MIPSN32-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
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; MIPSN32-NEXT: .cfi_offset 31, -8
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; MIPSN32-NEXT: jal __powisf2
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; MIPSN32-NEXT: sll $5, $5, 0
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; MIPSN32-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
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; MIPSN32-NEXT: jr $ra
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; MIPSN32-NEXT: addiu $sp, $sp, 16
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%1 = tail call float @llvm.powi.f32(float %value, i32 %power)
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ret float %1
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}
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