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30264d4391
As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
58 lines
2.1 KiB
LLVM
58 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s
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define <4 x double> @test_x86_avx_blend_pd_256(<4 x double> %a0) {
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; CHECK-LABEL: test_x86_avx_blend_pd_256:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%1 = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a0, i32 7)
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ret <4 x double> %1
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}
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define <8 x float> @test_x86_avx_blend_ps_256(<8 x float> %a0) {
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; CHECK-LABEL: test_x86_avx_blend_ps_256:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%1 = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a0, i32 7)
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ret <8 x float> %1
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}
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define <4 x double> @test2_x86_avx_blend_pd_256(<4 x double> %a0, <4 x double> %a1) {
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; CHECK-LABEL: test2_x86_avx_blend_pd_256:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%1 = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a1, i32 0)
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ret <4 x double> %1
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}
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define <8 x float> @test2_x86_avx_blend_ps_256(<8 x float> %a0, <8 x float> %a1) {
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; CHECK-LABEL: test2_x86_avx_blend_ps_256:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%1 = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a1, i32 0)
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ret <8 x float> %1
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}
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define <4 x double> @test3_x86_avx_blend_pd_256(<4 x double> %a0, <4 x double> %a1) {
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; CHECK-LABEL: test3_x86_avx_blend_pd_256:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovaps %ymm1, %ymm0
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; CHECK-NEXT: retq
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%1 = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a1, i32 -1)
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ret <4 x double> %1
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}
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define <8 x float> @test3_x86_avx_blend_ps_256(<8 x float> %a0, <8 x float> %a1) {
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; CHECK-LABEL: test3_x86_avx_blend_ps_256:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovaps %ymm1, %ymm0
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; CHECK-NEXT: retq
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%1 = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a1, i32 -1)
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ret <8 x float> %1
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}
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declare <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double>, <4 x double>, i32)
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declare <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float>, <8 x float>, i32)
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