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https://github.com/RPCS3/llvm-mirror.git
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ca0f4dc4f0
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
64 lines
1.4 KiB
LLVM
64 lines
1.4 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
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define i32 @t1(i32 %c) nounwind readnone {
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entry:
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; CHECK: @t1
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; CHECK: and w0, w0, #0x1
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; CHECK: subs w0, w0, #0
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; CHECK: csel w0, w{{[0-9]+}}, w{{[0-9]+}}, ne
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%0 = icmp sgt i32 %c, 1
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%1 = select i1 %0, i32 123, i32 357
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ret i32 %1
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}
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define i64 @t2(i32 %c) nounwind readnone {
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entry:
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; CHECK: @t2
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; CHECK: and w0, w0, #0x1
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; CHECK: subs w0, w0, #0
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; CHECK: csel x0, x{{[0-9]+}}, x{{[0-9]+}}, ne
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%0 = icmp sgt i32 %c, 1
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%1 = select i1 %0, i64 123, i64 357
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ret i64 %1
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}
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define i32 @t3(i1 %c, i32 %a, i32 %b) nounwind readnone {
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entry:
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; CHECK: @t3
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; CHECK: and w0, w0, #0x1
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; CHECK: subs w0, w0, #0
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; CHECK: csel w0, w{{[0-9]+}}, w{{[0-9]+}}, ne
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%0 = select i1 %c, i32 %a, i32 %b
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ret i32 %0
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}
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define i64 @t4(i1 %c, i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK: @t4
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; CHECK: and w0, w0, #0x1
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; CHECK: subs w0, w0, #0
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; CHECK: csel x0, x{{[0-9]+}}, x{{[0-9]+}}, ne
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%0 = select i1 %c, i64 %a, i64 %b
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ret i64 %0
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}
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define float @t5(i1 %c, float %a, float %b) nounwind readnone {
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entry:
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; CHECK: @t5
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; CHECK: and w0, w0, #0x1
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; CHECK: subs w0, w0, #0
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; CHECK: fcsel s0, s0, s1, ne
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%0 = select i1 %c, float %a, float %b
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ret float %0
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}
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define double @t6(i1 %c, double %a, double %b) nounwind readnone {
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entry:
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; CHECK: @t6
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; CHECK: and w0, w0, #0x1
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; CHECK: subs w0, w0, #0
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; CHECK: fcsel d0, d0, d1, ne
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%0 = select i1 %c, double %a, double %b
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ret double %0
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}
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