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226 lines
8.6 KiB
C++
226 lines
8.6 KiB
C++
//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TwoAddress instruction pass which is used
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// by most register allocators. Two-Address instructions are rewritten
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// from:
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//
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// A = B op C
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//
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// to:
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//
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// A = B
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// A op= C
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//
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// Note that if a register allocator chooses to use this pass, that it
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// has to be capable of handling the non-SSA nature of these rewritten
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// virtual registers.
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//
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// It is also worth noting that the duplicate operand of the two
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// address instruction is removed.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "twoaddrinstr"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
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STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
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STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
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namespace {
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struct VISIBILITY_HIDDEN TwoAddressInstructionPass
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: public MachineFunctionPass {
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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/// runOnMachineFunction - pass entry point
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bool runOnMachineFunction(MachineFunction&);
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};
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RegisterPass<TwoAddressInstructionPass>
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X("twoaddressinstruction", "Two-Address instruction pass");
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}
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const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo();
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void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<LiveVariables>();
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AU.addPreserved<LiveVariables>();
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AU.addPreservedID(PHIEliminationID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// runOnMachineFunction - Reduce two-address instructions to two
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/// operands.
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///
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bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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DOUT << "Machine Function\n";
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const TargetMachine &TM = MF.getTarget();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const MRegisterInfo &MRI = *TM.getRegisterInfo();
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LiveVariables &LV = getAnalysis<LiveVariables>();
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bool MadeChange = false;
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DOUT << "********** REWRITING TWO-ADDR INSTRS **********\n";
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DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
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for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
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mbbi != mbbe; ++mbbi) {
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for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
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mi != me; ++mi) {
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const TargetInstrDescriptor *TID = mi->getInstrDescriptor();
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bool FirstTied = true;
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for (unsigned si = 1, e = TID->numOperands; si < e; ++si) {
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int ti = TID->getOperandConstraint(si, TOI::TIED_TO);
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if (ti == -1)
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continue;
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if (FirstTied) {
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++NumTwoAddressInstrs;
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DOUT << '\t'; DEBUG(mi->print(*cerr.stream(), &TM));
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}
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FirstTied = false;
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assert(mi->getOperand(si).isRegister() && mi->getOperand(si).getReg() &&
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mi->getOperand(si).isUse() && "two address instruction invalid");
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// if the two operands are the same we just remove the use
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// and mark the def as def&use, otherwise we have to insert a copy.
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if (mi->getOperand(ti).getReg() != mi->getOperand(si).getReg()) {
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// rewrite:
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// a = b op c
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// to:
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// a = b
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// a = a op c
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unsigned regA = mi->getOperand(ti).getReg();
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unsigned regB = mi->getOperand(si).getReg();
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assert(MRegisterInfo::isVirtualRegister(regA) &&
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MRegisterInfo::isVirtualRegister(regB) &&
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"cannot update physical register live information");
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#ifndef NDEBUG
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// First, verify that we don't have a use of a in the instruction (a =
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// b + a for example) because our transformation will not work. This
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// should never occur because we are in SSA form.
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for (unsigned i = 0; i != mi->getNumOperands(); ++i)
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assert((int)i == ti ||
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!mi->getOperand(i).isRegister() ||
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mi->getOperand(i).getReg() != regA);
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#endif
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// If this instruction is not the killing user of B, see if we can
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// rearrange the code to make it so. Making it the killing user will
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// allow us to coalesce A and B together, eliminating the copy we are
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// about to insert.
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if (!LV.KillsRegister(mi, regB)) {
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// If this instruction is commutative, check to see if C dies. If
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// so, swap the B and C operands. This makes the live ranges of A
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// and C joinable.
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// FIXME: This code also works for A := B op C instructions.
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if ((TID->Flags & M_COMMUTABLE) && mi->getNumOperands() == 3) {
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assert(mi->getOperand(3-si).isRegister() &&
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"Not a proper commutative instruction!");
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unsigned regC = mi->getOperand(3-si).getReg();
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if (LV.KillsRegister(mi, regC)) {
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DOUT << "2addr: COMMUTING : " << *mi;
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MachineInstr *NewMI = TII.commuteInstruction(mi);
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if (NewMI == 0) {
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DOUT << "2addr: COMMUTING FAILED!\n";
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} else {
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DOUT << "2addr: COMMUTED TO: " << *NewMI;
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// If the instruction changed to commute it, update livevar.
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if (NewMI != mi) {
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LV.instructionChanged(mi, NewMI); // Update live variables
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mbbi->insert(mi, NewMI); // Insert the new inst
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mbbi->erase(mi); // Nuke the old inst.
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mi = NewMI;
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}
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++NumCommuted;
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regB = regC;
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goto InstructionRearranged;
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}
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}
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}
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// If this instruction is potentially convertible to a true
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// three-address instruction,
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if (TID->Flags & M_CONVERTIBLE_TO_3_ADDR)
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// FIXME: This assumes there are no more operands which are tied
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// to another register.
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#ifndef NDEBUG
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for (unsigned i = si+1, e = TID->numOperands; i < e; ++i)
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assert(TID->getOperandConstraint(i, TOI::TIED_TO) == -1);
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#endif
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if (MachineInstr *New = TII.convertToThreeAddress(mbbi, mi, LV)) {
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DOUT << "2addr: CONVERTING 2-ADDR: " << *mi;
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DOUT << "2addr: TO 3-ADDR: " << *New;
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mbbi->erase(mi); // Nuke the old inst.
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mi = New;
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++NumConvertedTo3Addr;
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// Done with this instruction.
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break;
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}
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}
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InstructionRearranged:
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const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
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MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
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MachineBasicBlock::iterator prevMi = prior(mi);
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DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM));
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// Update live variables for regA
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LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
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varInfo.DefInst = prevMi;
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// update live variables for regB
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if (LV.removeVirtualRegisterKilled(regB, mbbi, mi))
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LV.addVirtualRegisterKilled(regB, prevMi);
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if (LV.removeVirtualRegisterDead(regB, mbbi, mi))
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LV.addVirtualRegisterDead(regB, prevMi);
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// replace all occurences of regB with regA
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for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
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if (mi->getOperand(i).isRegister() &&
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mi->getOperand(i).getReg() == regB)
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mi->getOperand(i).setReg(regA);
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}
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}
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assert(mi->getOperand(ti).isDef() && mi->getOperand(si).isUse());
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mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
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MadeChange = true;
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DOUT << "\t\trewrite to:\t"; DEBUG(mi->print(*cerr.stream(), &TM));
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}
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}
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}
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return MadeChange;
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}
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