Tim Northover aebb01e004 GlobalISel: implement low-level type with just size & vector lanes. ... This should be all the low-level instruction selection needs to determine how to implement an operation, with the remaining context taken from the opcode (e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math). llvm-svn: 276158		2016-07-20 19:09:30 +00:00
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AArch64	GlobalISel: implement low-level type with just size & vector lanes.	2016-07-20 19:09:30 +00:00
AMDGPU	GlobalISel: implement low-level type with just size & vector lanes.	2016-07-20 19:09:30 +00:00
ARM	[ARM] Skip inline asm memory operands in DAGToDAGISel	2016-07-20 09:48:24 +00:00
BPF
Generic
Hexagon	[Hexagon] Handle returning small structures by value	2016-07-18 17:30:41 +00:00
Inputs
Lanai
Mips	Revert "RegScavenging: Add scavengeRegisterBackwards()"	2016-07-20 00:21:32 +00:00
MIR	GlobalISel: implement low-level type with just size & vector lanes.	2016-07-20 19:09:30 +00:00
MSP430
NVPTX	[NVPTX] deal with all aggregate return types.	2016-07-20 18:39:52 +00:00
PowerPC	Revert "RegScavenging: Add scavengeRegisterBackwards()"	2016-07-20 00:21:32 +00:00
SPARC
SystemZ	Revert "RegScavenging: Add scavengeRegisterBackwards()"	2016-07-20 00:21:32 +00:00
Thumb	Revert "RegScavenging: Add scavengeRegisterBackwards()"	2016-07-20 00:21:32 +00:00
Thumb2
WebAssembly
WinEH
X86	[X86][AVX512] Added AVX512 subvector broadcast tests	2016-07-19 17:04:28 +00:00
XCore