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https://github.com/RPCS3/llvm-mirror.git
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c2664c73ba
This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188
47 lines
1.5 KiB
C++
47 lines
1.5 KiB
C++
//===-- RISCVTargetMachine.h - Define TargetMachine for RISCV ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the RISCV specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVTARGETMACHINE_H
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#define LLVM_LIB_TARGET_RISCV_RISCVTARGETMACHINE_H
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class RISCVTargetMachine : public LLVMTargetMachine {
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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RISCVSubtarget Subtarget;
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public:
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RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT);
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const RISCVSubtarget *getSubtargetImpl(const Function &) const override {
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return &Subtarget;
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}
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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TargetLoweringObjectFile *getObjFileLowering() const override {
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return TLOF.get();
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}
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};
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}
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#endif
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