llvm-mirror

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History

Evan Cheng 13cc34e91b Scale 1 is always ok. llvm-svn: 35407		2007-03-28 01:55:52 +00:00
..
SelectionDAG	Scale 1 is always ok.	2007-03-28 01:55:52 +00:00
AsmPrinter.cpp
BranchFolding.cpp
DwarfWriter.cpp
ELFWriter.cpp
ELFWriter.h
IntrinsicLowering.cpp
LiveInterval.cpp
LiveIntervalAnalysis.cpp	Fix for PR1279. Dead def has a live interval of length 1. Copy coalescing should	2007-03-28 01:30:37 +00:00
LiveVariables.cpp
LLVMTargetMachine.cpp
MachineBasicBlock.cpp
MachineFunction.cpp
MachineInstr.cpp	Change findRegisterUseOperand() to return operand index instead.	2007-03-26 22:37:45 +00:00
MachineModuleInfo.cpp
MachinePassRegistry.cpp
MachOWriter.cpp
MachOWriter.h
Makefile
Passes.cpp
PHIElimination.cpp
PhysRegTracker.h
PrologEpilogInserter.cpp
README.txt	Potential spiller improvement.	2007-03-20 22:22:38 +00:00
RegAllocLinearScan.cpp
RegAllocLocal.cpp
RegAllocSimple.cpp
RegisterScavenging.cpp	Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable to	2007-03-26 22:23:54 +00:00
TwoAddressInstructionPass.cpp
UnreachableBlockElim.cpp
VirtRegMap.cpp	Don't call getOperandConstraint() if operand index is greater than	2007-03-27 00:48:28 +00:00
VirtRegMap.h

README.txt

Common register allocation / spilling problem:

	mul lr, r4, lr
	str lr, [sp, #+52]
	ldr lr, [r1, #+32]
	sxth r3, r3
	ldr r4, [sp, #+52]
	mla r4, r3, lr, r4

can be:

	mul lr, r4, lr
        mov r4, lr
	str lr, [sp, #+52]
	ldr lr, [r1, #+32]
	sxth r3, r3
	mla r4, r3, lr, r4

and then "merge" mul and mov:

	mul r4, r4, lr
	str lr, [sp, #+52]
	ldr lr, [r1, #+32]
	sxth r3, r3
	mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.