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2b2723c653
Implement fetch_<op>/fetch_and_<op>/exchange/compare-and-exchange instructions for BPF. Specially, the following gcc intrinsics are implemented. __sync_fetch_and_add (32, 64) __sync_fetch_and_sub (32, 64) __sync_fetch_and_and (32, 64) __sync_fetch_and_or (32, 64) __sync_fetch_and_xor (32, 64) __sync_lock_test_and_set (32, 64) __sync_val_compare_and_swap (32, 64) For __sync_fetch_and_sub, internally, it is implemented as a negation followed by __sync_fetch_and_add. For __sync_lock_test_and_set, despite its name, it actually does an atomic exchange and return the old content. https://gcc.gnu.org/onlinedocs/gcc-4.1.1/gcc/Atomic-Builtins.html For intrinsics like __sync_{add,sub}_and_fetch and __sync_bool_compare_and_swap, the compiler is able to generate codes using __sync_fetch_and_{add,sub} and __sync_val_compare_and_swap. Similar to xadd, atomic xadd, xor and xxor (atomic_<op>) instructions are added for atomic operations which do not have return values. LLVM will check the return value for __sync_fetch_and_{add,and,or,xor}. If the return value is used, instructions atomic_fetch_<op> will be used. Otherwise, atomic_<op> instructions will be used. All new instructions only support 64bit and 32bit with alu32 mode. old xadd instruction still supports 32bit without alu32 mode. For encoding, please take a look at test atomics_2.ll. Differential Revision: https://reviews.llvm.org/D72184
25 lines
843 B
LLVM
25 lines
843 B
LLVM
; RUN: llc < %s -march=bpfel -verify-machineinstrs -show-mc-encoding | FileCheck %s
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; RUN: llc < %s -march=bpfel -verify-machineinstrs -show-mc-encoding -mcpu=v3 | FileCheck --check-prefix=CHECK-V3 %s
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; CHECK-LABEL: test_load_add_32
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; CHECK: lock *(u32 *)(r1 + 0) += r2
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; CHECK: encoding: [0xc3,0x21
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; CHECK-V3: lock *(u32 *)(r1 + 0) += w2
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; CHECK-V3: encoding: [0xc3,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
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define void @test_load_add_32(i32* %p, i32 zeroext %v) {
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entry:
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atomicrmw add i32* %p, i32 %v seq_cst
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ret void
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}
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; CHECK-LABEL: test_load_add_64
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; CHECK: lock *(u64 *)(r1 + 0) += r2
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; CHECK: encoding: [0xdb,0x21
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; CHECK-V3: lock *(u64 *)(r1 + 0) += r2
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; CHECK-V3: encoding: [0xdb,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
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define void @test_load_add_64(i64* %p, i64 zeroext %v) {
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entry:
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atomicrmw add i64* %p, i64 %v seq_cst
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ret void
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}
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