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llvm-mirror/test/CodeGen/Hexagon/bit-extract-off.ll
Sumanth Gundapaneni 262321d1ff [Hexagon] New HVX target features.
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"

For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"

Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.

Differential Revision: https://reviews.llvm.org/D38851

llvm-svn: 316101
2017-10-18 18:07:07 +00:00

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LLVM

; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: extractu(r1,#31,#0)
; In the IR this was an extract of 31 bits starting at position 32 in r1:0.
; When mapping it to an extract from r1, the offset was not reset to 0, and
; we had "extractu(r1,#31,#32)".
target triple = "hexagon"
define hidden i32 @fred([101 x double]* %a0, i32 %a1, i32* %a2, i32* %a3) #0 {
b4:
br label %b5
b5: ; preds = %b5, %b4
%v6 = call double @fabs(double undef) #1
store double %v6, double* undef, align 8
br label %b5
}
declare double @fabs(double) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }