Ayman Musa 144efa4313 [X86][AVX512] Adding new LLVM TableGen backend which generates the EVEX2VEX compressing tables. ... X86EvexToVex machine instruction pass compresses EVEX encoded instructions by replacing them with their identical VEX encoded instructions when possible. It uses manually supported 2 large tables that map the EVEX instructions to their VEX ideticals. This TableGen backend replaces the tables by automatically generating them. Differential Revision: https://reviews.llvm.org/D30451 llvm-svn: 297127		2017-03-07 08:11:19 +00:00
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BackEnds.rst	[X86][AVX512] Adding new LLVM TableGen backend which generates the EVEX2VEX compressing tables.	2017-03-07 08:11:19 +00:00
Deficiencies.rst	Re-factor TableGen docs	2014-03-20 16:08:34 +00:00
index.rst	[docs] Fixing Sphinx warnings to unclog the buildbot	2016-07-20 12:16:38 +00:00
LangIntro.rst	[Docs][TableGen] Remove reference to tablegen supporting octal integers. It doesn't and hasn't for at least 9 years.	2016-11-18 02:28:50 +00:00
LangRef.rst	TableGen: Add operator !or	2016-11-15 06:49:28 +00:00