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llvm-mirror/test
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Ayke van Laethem 8dc0516b44 [AVR] Fix def state of operands 
Some instructions (especially mov+pop instructions) were setting the
wrong operands. For example, the pop instruction had the register set as
a source operand while it is a destination operand (the value is loaded
into the register).

I have found these issues using the machine verifier and using manual
code inspection.

Differential Revision: https://reviews.llvm.org/D97159
2021-03-03 15:36:05 +01:00
..
Analysis [TTI] Consider select form of and/or i1 as having arithmetic cost 2021-03-02 02:18:19 +09:00
Assembler
Bindings
Bitcode Add auto-upgrade support for annotation intrinsics 2021-02-22 15:42:16 -08:00
BugPoint
CodeGen [AVR] Fix def state of operands 2021-03-03 15:36:05 +01:00
DebugInfo Revert "Use the default seed value for djb hash for StringMap" 2021-03-01 14:00:39 +01:00
Demangle
Examples Revert "patch" it wass my mistake inusing git 2021-02-24 11:06:16 +05:30
ExecutionEngine [Orc] Extend lli debug support tests to JITLink 2021-03-02 15:07:36 +01:00
Feature
FileCheck [FileCheck] Do not skip end of line in diagnostics 2021-03-03 08:20:39 +00:00
Instrumentation [dfsan] Propagate origin tracking at load 2021-03-03 04:32:30 +00:00
Integer
JitListener
Linker [llvm-link] fix IRMover returning wrong modified vector type 2021-02-22 11:29:42 +00:00
LTO
MachineVerifier GlobalISel: Verify G_CONCAT_VECTORS has at least 2 sources 2021-03-01 09:10:36 -05:00
MC [AVR] Add register aliases XL, YH, etc 2021-03-03 15:36:05 +01:00
Object
ObjectYAML Add more historic DWARF vendor extensions 2021-02-25 15:09:42 -08:00
Other [opt] Error if -debug-pass is specified alongside the new PM 2021-03-02 15:59:28 -08:00
Reduce
SafepointIRVerifier
Support
SymbolRewriter
TableGen [TableGen] Add IntrNoMerge as intrinsic property 2021-03-02 09:04:50 -08:00
ThinLTO/X86 [WPD] Fix handling of pure virtual base class 2021-02-23 16:07:09 -08:00
tools Revert "Use the default seed value for djb hash for StringMap" 2021-03-01 14:00:39 +01:00
Transforms [Instcombine][NFC]Simplify logical reductions tests, NFC. 2021-03-02 08:27:42 -08:00
Unit
Verifier [IR] restrict vector reduction intrinsic types 2021-02-21 12:37:00 -05:00
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg.py
lit.site.cfg.py.in
TestRunner.sh