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d16aaccb05
LDM/STM instructions can run one cycle faster on some ARM processors if the memory address is 64-bit aligned. Radar 8489376. llvm-svn: 115047
43 lines
708 B
LLVM
43 lines
708 B
LLVM
; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=ELF
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; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
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@a = global i1 true
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; no alignment
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@b = global i8 1
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; no alignment
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@c = global i16 2
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;ELF: .align 1
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;ELF: c:
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;DARWIN: .align 1
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;DARWIN: _c:
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@d = global i32 3
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;ELF: .align 2
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;ELF: d:
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;DARWIN: .align 2
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;DARWIN: _d:
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@e = global i64 4
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;ELF: .align 3
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;ELF: e
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;DARWIN: .align 3
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;DARWIN: _e:
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@f = global float 5.0
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;ELF: .align 2
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;ELF: f:
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;DARWIN: .align 2
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;DARWIN: _f:
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@g = global double 6.0
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;ELF: .align 3
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;ELF: g:
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;DARWIN: .align 3
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;DARWIN: _g:
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@bar = common global [75 x i8] zeroinitializer, align 128
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;ELF: .comm bar,75,128
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;DARWIN: .comm _bar,75,7
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