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Sanjay Patel 1483c5f9fd [x86] form reduction intrinsics from vectorizers instead of raw IR
Motivating examples are seen in the PhaseOrdering tests based on:
https://bugs.llvm.org/show_bug.cgi?id=43953#c2 - if we have
intrinsics there, some pass can fold them.

The intrinsics are still named "experimental" at this point, but
if there is no fallout from this patch, that will be a good
indicator that it is safe to finalize them.

Differential Revision: https://reviews.llvm.org/D80867
2020-06-05 12:38:49 -04:00
benchmarks
bindings Fix go bindings after FixedVectorType -> VectorType change. 2020-05-15 16:37:57 -07:00
cmake Remove SVN logic from find_first_existing_vc_file 2020-05-29 20:31:55 +05:30
docs Fix a typo in AMDGPU docs 2020-06-05 13:30:17 +00:00
examples StoreInst should store Align, not MaybeAlign 2020-05-15 12:26:58 -07:00
include Revert "[CodeGen][SVE] Calculate correct type legalization for scalable vectors." 2020-06-05 16:03:52 +01:00
lib [x86] form reduction intrinsics from vectorizers instead of raw IR 2020-06-05 12:38:49 -04:00
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test [x86] form reduction intrinsics from vectorizers instead of raw IR 2020-06-05 12:38:49 -04:00
tools [dsymutil] Don't emit N_AST symbol entries in the Mach-O companion file 2020-06-05 08:42:18 -07:00
unittests Revert "[CodeGen][SVE] Calculate correct type legalization for scalable vectors." 2020-06-05 16:03:52 +01:00
utils [gn build] (manually) port a6fcf5ca033 2020-06-05 12:32:23 -04:00
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CMakeLists.txt Automatically configure MLIR when flang is enabled 2020-05-27 07:31:49 +00:00
CODE_OWNERS.TXT Add self as code owner for SCEV and IndVars 2020-05-26 17:35:54 -07:00
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