1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 19:42:54 +02:00
llvm-mirror/test/CodeGen/Mips/llvm-ir
Daniel Sanders 14a7ad6b92 [mips] Don't derive the default ABI from the CPU in the backend.
Summary:
The backend has no reason to behave like a driver and should generally do
as it's told (and error out if it can't) instead of trying to figure out
what the API user meant. The default ABI is still derived from the arch
component as a concession to backwards compatibility.

API-users that previously passed an explicit CPU and a triple that was
inconsistent with the CPU (e.g. mips-linux-gnu and mips64r2) may get a
different ABI to what they got before. However, it's expected that there
are no such users on the basis that CodeGen has been asserting that the
triple is consistent with the selected ABI for several releases. API-users
that were consistent or passed '' or 'generic' as the CPU will see no
difference.

Reviewers: sdardis, rafael

Subscribers: rafael, dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D21466

llvm-svn: 273557
2016-06-23 12:42:53 +00:00
..
add.ll [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
addrspacecast.ll
and.ll [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
ashr.ll [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions 2016-06-15 07:46:24 +00:00
atomicrmx.ll [mips] Define patterns for the atomic_{load,store}_{8,16,32,64} nodes. 2015-11-06 12:07:20 +00:00
call.ll Summary: 2016-04-14 13:43:17 +00:00
extractelement.ll Fix vector splitting for extract_vector_elt and vector elements of <8-bits. 2015-09-09 09:53:20 +00:00
indirectbr.ll Summary: 2016-04-14 13:43:17 +00:00
lh_lhu.ll [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
load-atomic.ll [mips] Define patterns for the atomic_{load,store}_{8,16,32,64} nodes. 2015-11-06 12:07:20 +00:00
lshr.ll [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions 2016-06-15 07:46:24 +00:00
mul.ll [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
not.ll [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
or.ll [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
ret.ll Summary: 2016-04-14 13:43:17 +00:00
sdiv.ll [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
select-dbl.ll [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions 2016-06-15 07:46:24 +00:00
select-flt.ll [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions 2016-06-15 07:46:24 +00:00
select-int.ll [mips][microMIPS] Add CodeGen support for SEL.*, SELEQZ, SELNEZ, SELEQZ.*, SELNEZ.* and CMP.condn.fmt instructions 2016-06-09 11:15:53 +00:00
shl.ll [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions 2016-06-15 07:46:24 +00:00
sqrt.ll [mips][microMIPS] Fix an issue with selecting sqrt instruction in LLVM backend 2015-10-06 15:17:25 +00:00
srem.ll [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
store-atomic.ll [mips] Define patterns for the atomic_{load,store}_{8,16,32,64} nodes. 2015-11-06 12:07:20 +00:00
sub.ll [mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU instructions 2016-04-27 11:31:44 +00:00
udiv.ll [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
urem.ll [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
xor.ll [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00