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cb60eaba94
This is a resubmit of r182877, which was reverted because it broken MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only enabled for iOS. I've CC'ed people from the original review and revert. FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl, but not MCJIT. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. All the tests also pass on x86 make check-all. I also re-ran the check-all tests that failed on ARM, and they all seem to pass. llvm-svn: 183966
52 lines
1.0 KiB
LLVM
52 lines
1.0 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
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define i32 @shl() nounwind ssp {
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entry:
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; ARM: shl
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; ARM: lsl r0, r0, #2
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%shl = shl i32 -1, 2
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ret i32 %shl
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}
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define i32 @shl_reg(i32 %src1, i32 %src2) nounwind ssp {
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entry:
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; ARM: shl_reg
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; ARM: lsl r0, r0, r1
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%shl = shl i32 %src1, %src2
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ret i32 %shl
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}
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define i32 @lshr() nounwind ssp {
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entry:
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; ARM: lshr
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; ARM: lsr r0, r0, #2
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%lshr = lshr i32 -1, 2
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ret i32 %lshr
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}
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define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind ssp {
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entry:
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; ARM: lshr_reg
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; ARM: lsr r0, r0, r1
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%lshr = lshr i32 %src1, %src2
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ret i32 %lshr
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}
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define i32 @ashr() nounwind ssp {
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entry:
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; ARM: ashr
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; ARM: asr r0, r0, #2
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%ashr = ashr i32 -1, 2
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ret i32 %ashr
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}
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define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind ssp {
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entry:
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; ARM: ashr_reg
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; ARM: asr r0, r0, r1
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%ashr = ashr i32 %src1, %src2
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ret i32 %ashr
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}
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