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cb60eaba94
This is a resubmit of r182877, which was reverted because it broken MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only enabled for iOS. I've CC'ed people from the original review and revert. FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl, but not MCJIT. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. All the tests also pass on x86 make check-all. I also re-ran the check-all tests that failed on ARM, and they all seem to pass. llvm-svn: 183966
185 lines
3.9 KiB
LLVM
185 lines
3.9 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
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; Very basic fast-isel functionality.
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define i32 @add(i32 %a, i32 %b) nounwind {
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entry:
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%a.addr = alloca i32, align 4
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%b.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr
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store i32 %b, i32* %b.addr
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%tmp = load i32* %a.addr
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%tmp1 = load i32* %b.addr
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%add = add nsw i32 %tmp, %tmp1
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ret i32 %add
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}
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; Check truncate to bool
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define void @test1(i32 %tmp) nounwind {
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entry:
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%tobool = trunc i32 %tmp to i1
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br i1 %tobool, label %if.then, label %if.end
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if.then: ; preds = %entry
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call void @test1(i32 0)
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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; ARM: test1:
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; ARM: tst r0, #1
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; THUMB: test1:
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; THUMB: tst.w r0, #1
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}
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; Check some simple operations with immediates
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define void @test2(i32 %tmp, i32* %ptr) nounwind {
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; THUMB: test2:
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; ARM: test2:
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b1:
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%a = add i32 %tmp, 4096
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store i32 %a, i32* %ptr
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br label %b2
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; THUMB: add.w {{.*}} #4096
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; ARM: add {{.*}} #4096
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b2:
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%b = add i32 %tmp, 4095
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store i32 %b, i32* %ptr
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br label %b3
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; THUMB: addw {{.*}} #4095
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; ARM: movw {{.*}} #4095
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; ARM: add
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b3:
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%c = or i32 %tmp, 4
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store i32 %c, i32* %ptr
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ret void
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; THUMB: orr {{.*}} #4
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; ARM: orr {{.*}} #4
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}
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define void @test3(i32 %tmp, i32* %ptr1, i16* %ptr2, i8* %ptr3) nounwind {
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; THUMB: test3:
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; ARM: test3:
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bb1:
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%a1 = trunc i32 %tmp to i16
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%a2 = trunc i16 %a1 to i8
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%a3 = trunc i8 %a2 to i1
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%a4 = zext i1 %a3 to i8
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store i8 %a4, i8* %ptr3
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%a5 = zext i8 %a4 to i16
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store i16 %a5, i16* %ptr2
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%a6 = zext i16 %a5 to i32
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store i32 %a6, i32* %ptr1
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br label %bb2
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; THUMB: and
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; THUMB: strb
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; THUMB: and{{.*}}, #255
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; THUMB: strh
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; THUMB: uxth
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; ARM: and
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; ARM: strb
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; ARM: and{{.*}}, #255
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; ARM: strh
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; ARM: uxth
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bb2:
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%b1 = trunc i32 %tmp to i16
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%b2 = trunc i16 %b1 to i8
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store i8 %b2, i8* %ptr3
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%b3 = sext i8 %b2 to i16
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store i16 %b3, i16* %ptr2
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%b4 = sext i16 %b3 to i32
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store i32 %b4, i32* %ptr1
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br label %bb3
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; THUMB: strb
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; THUMB: sxtb
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; THUMB: strh
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; THUMB: sxth
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; ARM: strb
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; ARM: sxtb
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; ARM: strh
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; ARM: sxth
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bb3:
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%c1 = load i8* %ptr3
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%c2 = load i16* %ptr2
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%c3 = load i32* %ptr1
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%c4 = zext i8 %c1 to i32
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%c5 = sext i16 %c2 to i32
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%c6 = add i32 %c4, %c5
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%c7 = sub i32 %c3, %c6
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store i32 %c7, i32* %ptr1
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ret void
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; THUMB: ldrb
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; THUMB: ldrh
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; THUMB: and{{.*}}, #255
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; THUMB: sxth
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; THUMB: add
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; THUMB: sub
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; ARM: ldrb
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; ARM: ldrh
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; ARM: and{{.*}}, #255
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; ARM: sxth
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; ARM: add
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; ARM: sub
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}
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; Check loads/stores with globals
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@test4g = external global i32
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define void @test4() {
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%a = load i32* @test4g
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%b = add i32 %a, 1
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store i32 %b, i32* @test4g
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ret void
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; Note that relocations are either movw/movt or constant pool
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; loads. Different platforms will select different approaches.
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; THUMB: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
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; THUMB: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}}
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; THUMB: ldr r0, [r0]
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; THUMB: ldr r1, [r0]
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; THUMB: adds r1, #1
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; THUMB: str r1, [r0]
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; ARM: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr r0, .LCPI)}}
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; ARM: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}}
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; ARM: ldr r0, [r0]
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; ARM: ldr r1, [r0]
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; ARM: add r1, r1, #1
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; ARM: str r1, [r0]
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}
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; ARM: @urem_fold
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; THUMB: @urem_fold
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; ARM: and r0, r0, #31
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; THUMB: and r0, r0, #31
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define i32 @urem_fold(i32 %a) nounwind {
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%rem = urem i32 %a, 32
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ret i32 %rem
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}
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define i32 @trap_intrinsic() noreturn nounwind {
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entry:
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; ARM: @trap_intrinsic
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; THUMB: @trap_intrinsic
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; ARM: trap
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; THUMB: trap
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tail call void @llvm.trap( )
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unreachable
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}
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declare void @llvm.trap() nounwind
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