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964ffa104f
Add pseudo conditional store instructions, so that we use:
branch foo:
store
foo:
instead of:
load
branch foo:
move
foo:
store
z196 has real 32-bit and 64-bit conditional stores, but we don't use
any z196 instructions yet.
llvm-svn: 185065
214 lines
5.5 KiB
LLVM
214 lines
5.5 KiB
LLVM
; Test f32 conditional stores that are presented as selects.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare void @foo(float *)
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; Test with the loaded value first.
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define void @f1(float *%ptr, float %alt, i32 %limit) {
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; CHECK: f1:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: ste %f0, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load float *%ptr
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%res = select i1 %cond, float %orig, float %alt
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store float %res, float *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f2(float *%ptr, float %alt, i32 %limit) {
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; CHECK: f2:
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; CHECK-NOT: %r2
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; CHECK: jnl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: ste %f0, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load float *%ptr
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%res = select i1 %cond, float %alt, float %orig
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store float %res, float *%ptr
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ret void
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}
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; Check the high end of the aligned STE range.
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define void @f3(float *%base, float %alt, i32 %limit) {
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; CHECK: f3:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: ste %f0, 4092(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr float *%base, i64 1023
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%cond = icmp ult i32 %limit, 42
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%orig = load float *%ptr
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%res = select i1 %cond, float %orig, float %alt
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store float %res, float *%ptr
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ret void
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}
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; Check the next word up, which should use STEY instead of STE.
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define void @f4(float *%base, float %alt, i32 %limit) {
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; CHECK: f4:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: stey %f0, 4096(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr float *%base, i64 1024
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%cond = icmp ult i32 %limit, 42
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%orig = load float *%ptr
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%res = select i1 %cond, float %orig, float %alt
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store float %res, float *%ptr
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ret void
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}
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; Check the high end of the aligned STEY range.
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define void @f5(float *%base, float %alt, i32 %limit) {
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; CHECK: f5:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: stey %f0, 524284(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr float *%base, i64 131071
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%cond = icmp ult i32 %limit, 42
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%orig = load float *%ptr
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%res = select i1 %cond, float %orig, float %alt
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store float %res, float *%ptr
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ret void
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f6(float *%base, float %alt, i32 %limit) {
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; CHECK: f6:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: agfi %r2, 524288
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; CHECK: ste %f0, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr float *%base, i64 131072
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%cond = icmp ult i32 %limit, 42
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%orig = load float *%ptr
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%res = select i1 %cond, float %orig, float %alt
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store float %res, float *%ptr
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ret void
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}
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; Check the low end of the STEY range.
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define void @f7(float *%base, float %alt, i32 %limit) {
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; CHECK: f7:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: stey %f0, -524288(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr float *%base, i64 -131072
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%cond = icmp ult i32 %limit, 42
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%orig = load float *%ptr
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%res = select i1 %cond, float %orig, float %alt
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store float %res, float *%ptr
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ret void
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f8(float *%base, float %alt, i32 %limit) {
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; CHECK: f8:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: agfi %r2, -524292
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; CHECK: ste %f0, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr float *%base, i64 -131073
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%cond = icmp ult i32 %limit, 42
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%orig = load float *%ptr
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%res = select i1 %cond, float %orig, float %alt
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store float %res, float *%ptr
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ret void
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}
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; Check that STEY allows an index.
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define void @f9(i64 %base, i64 %index, float %alt, i32 %limit) {
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; CHECK: f9:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: stey %f0, 4096(%r3,%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%add1 = add i64 %base, %index
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%add2 = add i64 %add1, 4096
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%ptr = inttoptr i64 %add2 to float *
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%cond = icmp ult i32 %limit, 42
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%orig = load float *%ptr
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%res = select i1 %cond, float %orig, float %alt
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store float %res, float *%ptr
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ret void
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}
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; Check that volatile loads are not matched.
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define void @f10(float *%ptr, float %alt, i32 %limit) {
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; CHECK: f10:
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; CHECK: le {{%f[0-5]}}, 0(%r2)
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; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
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; CHECK: [[LABEL]]:
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; CHECK: ste {{%f[0-5]}}, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load volatile float *%ptr
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%res = select i1 %cond, float %orig, float %alt
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store float %res, float *%ptr
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ret void
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}
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; ...likewise stores. In this case we should have a conditional load into %f0.
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define void @f11(float *%ptr, float %alt, i32 %limit) {
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; CHECK: f11:
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; CHECK: jnl [[LABEL:[^ ]*]]
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; CHECK: le %f0, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: ste %f0, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load float *%ptr
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%res = select i1 %cond, float %orig, float %alt
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store volatile float %res, float *%ptr
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ret void
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}
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; Try a frame index base.
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define void @f12(float %alt, i32 %limit) {
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; CHECK: f12:
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; CHECK: brasl %r14, foo@PLT
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; CHECK-NOT: %r15
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r15
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; CHECK: ste {{%f[0-9]+}}, {{[0-9]+}}(%r15)
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; CHECK: [[LABEL]]:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: br %r14
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%ptr = alloca float
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call void @foo(float *%ptr)
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%cond = icmp ult i32 %limit, 42
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%orig = load float *%ptr
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%res = select i1 %cond, float %orig, float %alt
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store float %res, float *%ptr
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call void @foo(float *%ptr)
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ret void
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}
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