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c7495a0fca
Add a mapping from register-based <INSN>R instructions to the corresponding memory-based <INSN>. Use it to cut down on the number of spill loads. Some instructions extend their operands from smaller fields, so this required a new TSFlags field to say how big the unextended operand is. This optimisation doesn't trigger for C(G)R and CL(G)R because in practice we always combine those instructions with a branch. Adding a test for every other case probably seems excessive, but it did catch a missed optimisation for DSGF (fixed in r185435). llvm-svn: 185529
140 lines
3.3 KiB
LLVM
140 lines
3.3 KiB
LLVM
; Test 64-bit ORs in which the second operand is variable.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i64 @foo()
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; Check OGR.
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define i64 @f1(i64 %a, i64 %b) {
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; CHECK: f1:
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; CHECK: ogr %r2, %r3
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; CHECK: br %r14
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%or = or i64 %a, %b
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ret i64 %or
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}
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; Check OG with no displacement.
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define i64 @f2(i64 %a, i64 *%src) {
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; CHECK: f2:
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; CHECK: og %r2, 0(%r3)
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; CHECK: br %r14
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%b = load i64 *%src
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%or = or i64 %a, %b
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ret i64 %or
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}
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; Check the high end of the aligned OG range.
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define i64 @f3(i64 %a, i64 *%src) {
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; CHECK: f3:
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; CHECK: og %r2, 524280(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 65535
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%b = load i64 *%ptr
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%or = or i64 %a, %b
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ret i64 %or
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}
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; Check the next doubleword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f4(i64 %a, i64 *%src) {
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; CHECK: f4:
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; CHECK: agfi %r3, 524288
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; CHECK: og %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 65536
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%b = load i64 *%ptr
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%or = or i64 %a, %b
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ret i64 %or
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}
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; Check the high end of the negative aligned OG range.
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define i64 @f5(i64 %a, i64 *%src) {
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; CHECK: f5:
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; CHECK: og %r2, -8(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -1
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%b = load i64 *%ptr
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%or = or i64 %a, %b
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ret i64 %or
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}
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; Check the low end of the OG range.
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define i64 @f6(i64 %a, i64 *%src) {
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; CHECK: f6:
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; CHECK: og %r2, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -65536
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%b = load i64 *%ptr
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%or = or i64 %a, %b
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ret i64 %or
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}
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; Check the next doubleword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f7(i64 %a, i64 *%src) {
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; CHECK: f7:
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; CHECK: agfi %r3, -524296
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; CHECK: og %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -65537
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%b = load i64 *%ptr
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%or = or i64 %a, %b
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ret i64 %or
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}
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; Check that OG allows an index.
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define i64 @f8(i64 %a, i64 %src, i64 %index) {
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; CHECK: f8:
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; CHECK: og %r2, 524280({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524280
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%ptr = inttoptr i64 %add2 to i64 *
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%b = load i64 *%ptr
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%or = or i64 %a, %b
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ret i64 %or
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}
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; Check that ORs of spilled values can use OG rather than OGR.
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define i64 @f9(i64 *%ptr0) {
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; CHECK: f9:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: og %r2, 160(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr i64 *%ptr0, i64 2
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%ptr2 = getelementptr i64 *%ptr0, i64 4
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%ptr3 = getelementptr i64 *%ptr0, i64 6
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%ptr4 = getelementptr i64 *%ptr0, i64 8
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%ptr5 = getelementptr i64 *%ptr0, i64 10
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%ptr6 = getelementptr i64 *%ptr0, i64 12
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%ptr7 = getelementptr i64 *%ptr0, i64 14
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%ptr8 = getelementptr i64 *%ptr0, i64 16
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%ptr9 = getelementptr i64 *%ptr0, i64 18
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%val0 = load i64 *%ptr0
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%val1 = load i64 *%ptr1
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%val2 = load i64 *%ptr2
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%val3 = load i64 *%ptr3
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%val4 = load i64 *%ptr4
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%val5 = load i64 *%ptr5
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%val6 = load i64 *%ptr6
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%val7 = load i64 *%ptr7
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%val8 = load i64 *%ptr8
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%val9 = load i64 *%ptr9
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%ret = call i64 @foo()
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%or0 = or i64 %ret, %val0
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%or1 = or i64 %or0, %val1
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%or2 = or i64 %or1, %val2
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%or3 = or i64 %or2, %val3
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%or4 = or i64 %or3, %val4
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%or5 = or i64 %or4, %val5
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%or6 = or i64 %or5, %val6
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%or7 = or i64 %or6, %val7
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%or8 = or i64 %or7, %val8
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%or9 = or i64 %or8, %val9
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ret i64 %or9
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}
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