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d49cb60862
Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
99 lines
3.1 KiB
YAML
99 lines
3.1 KiB
YAML
# RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \
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# RUN: -stop-after=finalize-isel -relocation-model=pic \
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# RUN: -o /dev/null %s
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# A simple test to show that we can parse the target specific flags: gpoff-hi,
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# gpoff-lo, got-call, got-disp.
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--- |
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@v = global i32 0, align 4
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@j = external global i32, align 4
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define i32 @_Z2k1i(i32 signext %asd) {
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entry:
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%call = tail call i32 @_Z1gi(i32 signext %asd)
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%add = add nsw i32 %call, %asd
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%0 = load i32, i32* @v, align 4
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%add1 = add nsw i32 %add, %0
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%1 = load i32, i32* @j, align 4
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%add2 = add nsw i32 %add1, %1
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ret i32 %add2
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}
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declare i32 @_Z1gi(i32 signext)
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...
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---
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name: _Z2k1i
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alignment: 8
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr64, preferred-register: '' }
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- { id: 1, class: gpr64, preferred-register: '' }
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- { id: 2, class: gpr64, preferred-register: '' }
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- { id: 3, class: gpr32, preferred-register: '' }
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- { id: 4, class: gpr32, preferred-register: '' }
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- { id: 5, class: gpr32, preferred-register: '' }
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- { id: 6, class: gpr64, preferred-register: '' }
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- { id: 7, class: gpr32, preferred-register: '' }
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- { id: 8, class: gpr32, preferred-register: '' }
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- { id: 9, class: gpr64, preferred-register: '' }
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- { id: 10, class: gpr32, preferred-register: '' }
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- { id: 11, class: gpr32, preferred-register: '' }
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- { id: 12, class: gpr64, preferred-register: '' }
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- { id: 13, class: gpr64, preferred-register: '' }
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liveins:
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- { reg: '$a0_64', virtual-reg: '%0' }
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- { reg: '$t9_64', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: true
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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liveins: $a0_64, $t9_64
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%12 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i
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%13 = DADDu %12, $t9_64
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%1 = DADDiu %13, target-flags(mips-gpoff-lo) @_Z2k1i
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%0 = COPY $a0_64
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ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
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%2 = LD %1, target-flags(mips-got-call) @_Z1gi :: (load 8 from call-entry @_Z1gi)
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$a0_64 = COPY %0
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$gp_64 = COPY %1
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JALR64Pseudo killed %2, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
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ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
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%3 = COPY $v0
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%4 = COPY %0.sub_32
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%5 = ADDu %3, killed %4
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%6 = LD %1, target-flags(mips-got-disp) @v :: (load 8 from got)
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%7 = LW killed %6, 0 :: (dereferenceable load 4 from @v)
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%8 = ADDu killed %5, killed %7
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%9 = LD %1, target-flags(mips-got-disp) @j :: (load 8 from got)
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%10 = LW killed %9, 0 :: (dereferenceable load 4 from @j)
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%11 = ADDu killed %8, killed %10
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$v0 = COPY %11
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RetRA implicit $v0
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...
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