Fraser Cormack 1540d39c62 [RISCV] Pattern-match more vector-splatted constants ... This patch extends the pattern-matching capability of vector-splatted constants. When illegally-typed constants are legalized they are canonically sign-extended to XLenVT. This preserves the sign and allows us to match simm5. If they were zero-extended for whatever reason we'd lose that ability: e.g. `(i8 -1) -> (XLenVT 255)` would not be matched under the current logic. To address this we first manually sign-extend the splatted constant from the vector element type to int64_t. This preserves the semantics while removing any implicitly-truncated bits. The corresponding logic for uimm5 was not updated, the rationale being that neither sign- nor zero-extending a legal uimm5 immediate should change that (unless we expect actual "garbage" upper bits). Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D93837		2020-12-28 07:11:10 +00:00
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AsmParser	[RISCV] Improve VMConstraint checking on more unary and nullary instructions.	2020-12-26 18:47:59 -08:00
Disassembler	[RISCV] Support Zfh half-precision floating-point extension.	2020-12-03 09:16:33 +08:00
MCTargetDesc	[RISCV] Move vtype decoding and printing from RISCVInstPrinter to RISCVBaseInfo. Share with the assembly parser's debug output	2020-12-14 10:50:26 -08:00
TargetInfo	llvmbuildectomy - replace llvm-build by plain cmake	2020-11-13 10:35:24 +01:00
Utils	[RISCV] Improve VMConstraint checking on more unary and nullary instructions.	2020-12-26 18:47:59 -08:00
CMakeLists.txt	[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.	2020-12-11 10:35:37 -08:00
RISCV.h	[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.	2020-12-11 10:35:37 -08:00
RISCV.td	[RISCV] V does not imply F.	2020-12-17 10:57:36 +08:00
RISCVAsmPrinter.cpp
RISCVCallingConv.td
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVCleanupVSETVLI.cpp	[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.	2020-12-11 10:35:37 -08:00
RISCVExpandAtomicPseudoInsts.cpp
RISCVExpandPseudoInsts.cpp	[RISCV] Initial infrastructure for code generation of the RISC-V V-extension	2020-12-04 11:39:30 -08:00
RISCVFrameLowering.cpp	[RISCV] Support Zfh half-precision floating-point extension.	2020-12-03 09:16:33 +08:00
RISCVFrameLowering.h
RISCVInstrFormats.td	[RISCV] Improve VMConstraint checking on more unary and nullary instructions.	2020-12-26 18:47:59 -08:00
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td
RISCVInstrInfo.cpp	[Target] Use llvm::erase_if (NFC)	2020-12-20 17:43:22 -08:00
RISCVInstrInfo.h	[RISCV] Don't include CodeGen layer files in MC layer	2020-11-12 07:45:38 -08:00
RISCVInstrInfo.td	[RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions	2020-12-10 19:25:51 +00:00
RISCVInstrInfoA.td
RISCVInstrInfoB.td	[RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions	2020-12-10 19:25:51 +00:00
RISCVInstrInfoC.td	[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump	2020-12-04 10:34:12 -08:00
RISCVInstrInfoD.td	[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.	2020-12-10 09:15:52 -08:00
RISCVInstrInfoF.td	[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.	2020-12-10 09:15:52 -08:00
RISCVInstrInfoM.td	[RISCV] Don't remove (and X, 0xffffffff) from inputs when matching RISCVISD::DIVUW/REMUW to 64-bit DIVU/REMU.	2020-11-26 23:15:41 -08:00
RISCVInstrInfoV.td	[RISCV] Improve VMConstraint checking on more unary and nullary instructions.	2020-12-26 18:47:59 -08:00
RISCVInstrInfoVPseudos.td	[RISCV] Define vector widening reduction intrinsic.	2020-12-26 21:42:30 +08:00
RISCVInstrInfoVSDPatterns.td	[RISCV] Add ISel support for RVV vector/scalar forms	2020-12-23 20:16:18 +00:00
RISCVInstrInfoZfh.td	[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.	2020-12-10 09:15:52 -08:00
RISCVInstructionSelector.cpp
RISCVISelDAGToDAG.cpp	[RISCV] Pattern-match more vector-splatted constants	2020-12-28 07:11:10 +00:00
RISCVISelDAGToDAG.h	[RISCV] Add ISel support for RVV vector/scalar forms	2020-12-23 20:16:18 +00:00
RISCVISelLowering.cpp	[Target] Use llvm::any_of (NFC)	2020-12-24 19:43:26 -08:00
RISCVISelLowering.h	[RISCV] Add ISel support for RVV vector/scalar forms	2020-12-23 20:16:18 +00:00
RISCVLegalizerInfo.cpp
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp	[RISCV] Basic jump table lowering	2020-12-22 15:05:54 +00:00
RISCVMergeBaseOffset.cpp	[RISCV] Support Zfh half-precision floating-point extension.	2020-12-03 09:16:33 +08:00
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp	[RISCV] Define the remaining vector fixed-point arithmetic intrinsics.	2020-12-20 22:57:07 -08:00
RISCVRegisterInfo.h
RISCVRegisterInfo.td	[RISCV] Define the remaining vector fixed-point arithmetic intrinsics.	2020-12-20 22:57:07 -08:00
RISCVSchedRocket.td
RISCVSchedSiFive7.td
RISCVSchedule.td
RISCVSubtarget.cpp
RISCVSubtarget.h	[RISCV] Support Zfh half-precision floating-point extension.	2020-12-03 09:16:33 +08:00
RISCVSystemOperands.td
RISCVTargetMachine.cpp	[RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.	2020-12-18 21:50:55 +00:00
RISCVTargetMachine.h	[RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.	2020-12-18 21:50:55 +00:00
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp
RISCVTargetTransformInfo.h