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9b6cc48b31
Summary: 1. Support pointer type as function argumnet and return value 2. G_STORE/G_LOAD - set legal action for i8/i16/i32/i64/f32/f64/vec128 3. RegisterBank - support typeless operations like G_STORE/G_LOAD, for scalar use GPR bank. 4. Support instruction selection for G_LOAD/G_STORE Reviewers: zvi, rovka, ab, qcolombet Reviewed By: rovka Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank Differential Revision: https://reviews.llvm.org/D30973 llvm-svn: 298609
105 lines
3.4 KiB
C++
105 lines
3.4 KiB
C++
//===- X86GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file defines all the static objects used by X86RegisterBankInfo.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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#error "You shouldn't build this"
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#endif
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#ifdef GET_TARGET_REGBANK_INFO_IMPL
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RegisterBankInfo::PartialMapping X86GenRegisterBankInfo::PartMappings[]{
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/* StartIdx, Length, RegBank */
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// GPR value
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{0, 8, X86::GPRRegBank}, // :0
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{0, 16, X86::GPRRegBank}, // :1
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{0, 32, X86::GPRRegBank}, // :2
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{0, 64, X86::GPRRegBank}, // :3
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// FR32/64 , xmm registers
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{0, 32, X86::VECRRegBank}, // :4
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{0, 64, X86::VECRRegBank}, // :5
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// VR128/256/512
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{0, 128, X86::VECRRegBank}, // :6
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{0, 256, X86::VECRRegBank}, // :7
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{0, 512, X86::VECRRegBank}, // :8
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};
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#endif // GET_TARGET_REGBANK_INFO_IMPL
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#ifdef GET_TARGET_REGBANK_INFO_CLASS
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enum PartialMappingIdx {
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PMI_None = -1,
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PMI_GPR8,
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PMI_GPR16,
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PMI_GPR32,
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PMI_GPR64,
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PMI_FP32,
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PMI_FP64,
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PMI_VEC128,
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PMI_VEC256,
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PMI_VEC512
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};
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#endif // GET_TARGET_REGBANK_INFO_CLASS
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#ifdef GET_TARGET_REGBANK_INFO_IMPL
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#define INSTR_3OP(INFO) INFO, INFO, INFO,
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#define BREAKDOWN(INDEX, NUM) \
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{ &X86GenRegisterBankInfo::PartMappings[INDEX], NUM }
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// ValueMappings.
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RegisterBankInfo::ValueMapping X86GenRegisterBankInfo::ValMappings[]{
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/* BreakDown, NumBreakDowns */
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// 3-operands instructions (all binary operations should end up with one of
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// those mapping).
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INSTR_3OP(BREAKDOWN(PMI_GPR8, 1)) // 0: GPR_8
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INSTR_3OP(BREAKDOWN(PMI_GPR16, 1)) // 3: GPR_16
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INSTR_3OP(BREAKDOWN(PMI_GPR32, 1)) // 6: GPR_32
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INSTR_3OP(BREAKDOWN(PMI_GPR64, 1)) // 9: GPR_64
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INSTR_3OP(BREAKDOWN(PMI_FP32, 1)) // 12: Fp32
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INSTR_3OP(BREAKDOWN(PMI_FP64, 1)) // 15: Fp64
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INSTR_3OP(BREAKDOWN(PMI_VEC128, 1)) // 18: Vec128
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INSTR_3OP(BREAKDOWN(PMI_VEC256, 1)) // 21: Vec256
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INSTR_3OP(BREAKDOWN(PMI_VEC512, 1)) // 24: Vec512
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};
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#undef INSTR_3OP
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#undef BREAKDOWN
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#endif // GET_TARGET_REGBANK_INFO_IMPL
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#ifdef GET_TARGET_REGBANK_INFO_CLASS
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enum ValueMappingIdx {
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VMI_None = -1,
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VMI_3OpsGpr8Idx = PMI_GPR8 * 3,
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VMI_3OpsGpr16Idx = PMI_GPR16 * 3,
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VMI_3OpsGpr32Idx = PMI_GPR32 * 3,
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VMI_3OpsGpr64Idx = PMI_GPR64 * 3,
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VMI_3OpsFp32Idx = PMI_FP32 * 3,
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VMI_3OpsFp64Idx = PMI_FP64 * 3,
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VMI_3OpsVec128Idx = PMI_VEC128 * 3,
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VMI_3OpsVec256Idx = PMI_VEC256 * 3,
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VMI_3OpsVec512Idx = PMI_VEC512 * 3,
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};
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#undef GET_TARGET_REGBANK_INFO_CLASS
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#endif // GET_TARGET_REGBANK_INFO_CLASS
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#ifdef GET_TARGET_REGBANK_INFO_IMPL
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#undef GET_TARGET_REGBANK_INFO_IMPL
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const RegisterBankInfo::ValueMapping *
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X86GenRegisterBankInfo::getValueMapping(PartialMappingIdx Idx,
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unsigned NumOperands) {
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// We can use VMI_3Ops Mapping for all the cases.
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if (NumOperands <= 3 && (Idx >= PMI_GPR8 && Idx <= PMI_VEC512))
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return &ValMappings[(unsigned)Idx * 3];
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llvm_unreachable("Unsupported PartialMappingIdx.");
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}
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#endif // GET_TARGET_REGBANK_INFO_IMPL
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