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562 lines
21 KiB
TableGen
562 lines
21 KiB
TableGen
//===- LanaiInstrFormats.td - Lanai Instruction Formats ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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class InstLanai<dag outs, dag ins, string asmstr, list<dag> pattern>
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: Instruction {
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field bits<32> Inst;
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field bits<32> SoftFail = 0;
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let Size = 4;
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let Namespace = "Lanai";
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let DecoderNamespace = "Lanai";
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bits<4> Opcode;
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let Inst{31 - 28} = Opcode;
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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}
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//------------------------------------------------------------------------------
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// Register Immediate (RI)
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//------------------------------------------------------------------------------
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// Encoding:
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// -----------------------------------------------------------------
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// |0.A.A.A| . . . . | . . . . |F.H| . . . . . . . . . . . . . . . |
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// -----------------------------------------------------------------
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// opcode Rd Rs1 constant (16)
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//
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// Action:
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// Rd <- Rs1 op constant
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//
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// Except for shift instructions, `H' determines whether the constant
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// is in the high (1) or low (0) word. The other halfword is 0x0000,
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// except for the `AND' instruction (`AAA' = 100), for which the other
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// halfword is 0xFFFF, and shifts (`AAA' = 111), for which the constant is
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// sign extended.
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//
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// `F' determines whether the instruction modifies (1) or does not
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// modify (0) the program flags.
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//
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// `AAA' specifies the operation: `add' (000), `addc' (001), `sub'
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// (010), `subb' (011), `and' (100), `or' (101), `xor' (110), or `shift'
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// (111). For the shift, `H' specifies a logical (0) or arithmetic (1)
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// shift. The amount and direction of the shift are determined by the
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// sign extended constant interpreted as a two's complement number. The
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// shift operation is defined only for the range of:
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// 31 ... 0 -1 ... -31
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// \ / \ /
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// left right
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// shift shift
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//
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// If and only if the `F' bit is 1, RI instructions modify the
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// condition bits, `Z' (Zero), `N' (Negative), `V' (oVerflow), and `C'
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// (Carry), according to the result. If the flags are updated, they are
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// updated as follows:
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// `Z'
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// is set if the result is zero and cleared otherwise.
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//
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// `N'
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// is set to the most significant bit of the result.
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//
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// `V'
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// For arithmetic instructions (`add', `addc', `sub', `subb') `V' is
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// set if the sign (most significant) bits of the input operands are
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// the same but different from the sign bit of the result and cleared
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// otherwise. For other RI instructions, `V' is cleared.
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//
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// `C'
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// For arithmetic instructions, `C' is set/cleared if there is/is_not
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// a carry generated out of the most significant when performing the
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// twos-complement addition (`sub(a,b) == a + ~b + 1', `subb(a,b) ==
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// a + ~b + `C''). For left shifts, `C' is set to the least
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// significant bit discarded by the shift operation. For all other
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// operations, `C' is cleared.
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//
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// A Jump is accomplished by `Rd' being `pc', and it has one shadow.
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//
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// The all-0s word is the instruction `R0 <- R0 + 0', which is a no-op.
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class InstRI<bits<3> op, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: InstLanai<outs, ins, asmstr, pattern>, Sched<[WriteALU]> {
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let Itinerary = IIC_ALU;
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bits<5> Rd;
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bits<5> Rs1;
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bit F;
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bit H;
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bits<16> imm16;
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let Opcode{3} = 0;
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let Opcode{2 - 0} = op;
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let Inst{27 - 23} = Rd;
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let Inst{22 - 18} = Rs1;
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let Inst{17} = F;
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let Inst{16} = H;
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let Inst{15 - 0} = imm16;
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}
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//------------------------------------------------------------------------------
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// Register Register (RR)
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//------------------------------------------------------------------------------
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// Encoding:
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// -----------------------------------------------------------------
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// |1.1.0.0| . . . . | . . . . |F.I| . . . . |B.B.B|J.J.J.J.J|D.D.D|
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// -----------------------------------------------------------------
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// opcode Rd Rs1 Rs2 \ operation /
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//
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// Action:
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// `Rd <- Rs1 op Rs2' iff condition DDDI is true.
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//
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// `DDDI' is as described for the BR instruction.
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//
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// `F' determines whether the instruction modifies (1) or does not
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// modify (0) the program flags.
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//
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// `BBB' determines the operation: `add' (000), `addc' (001), `sub'
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// (010), `subb' (011), `and' (100), `or' (101), `xor' (110), or "special"
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// (111). The `JJJJJ' field is irrelevant except for special.
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//
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// `JJJJJ' determines which special operation is performed. `10---'
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// is a logical shift, and `11---' is an arithmetic shift, and ‘00000` is
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// the SELECT operation. The amount and direction of the shift are
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// determined by the contents of `Rs2' interpreted as a two's complement
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// number (in the same way as shifts in the Register-Immediate
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// instructions in *Note RI::). For the SELECT operation, Rd gets Rs1 if
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// condition DDDI is true, Rs2 otherwise. All other `JJJJJ' combinations
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// are reserved for instructions that may be defined in the future.
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//
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// If the `F' bit is 1, RR instructions modify the condition bits, `Z'
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// (Zero), `N' (Negative), `V' (oVerflow), and `C' (Carry), according to
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// the result. All RR instructions modify the `Z', `N', and `V' flags.
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// Except for arithmetic instructions (`add', `addc', `sub', `subb'), `V'
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// is cleared. Only arithmetic instructions and shifts modify `C'. Right
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// shifts clear C.
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//
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// DDDI is as described in the table for the BR instruction and only used for
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// the select instruction.
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//
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// A Jump is accomplished by `Rd' being `pc', and it has one shadow.
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class InstRR<bits<3> op, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: InstLanai<outs, ins, asmstr, pattern>, Sched<[WriteALU]> {
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let Itinerary = IIC_ALU;
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bits<5> Rd;
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bits<5> Rs1;
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bits<5> Rs2;
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bit F;
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bits<4> DDDI;
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bits<5> JJJJJ;
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let Opcode = 0b1100;
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let Inst{27 - 23} = Rd;
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let Inst{22 - 18} = Rs1;
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let Inst{17} = F;
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let Inst{16} = DDDI{0};
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let Inst{15 - 11} = Rs2;
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let Inst{10 - 8} = op;
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let Inst{7 - 3} = JJJJJ;
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let Inst{2 - 0} = DDDI{3 - 1};
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}
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//------------------------------------------------------------------------------
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// Register Memory (RM)
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//------------------------------------------------------------------------------
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// Encoding:
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// -----------------------------------------------------------------
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// |1.0.0.S| . . . . | . . . . |P.Q| . . . . . . . . . . . . . . . |
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// -----------------------------------------------------------------
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// opcode Rd Rs1 constant (16)
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//
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// Action:
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// Rd <- Memory(ea) (Load) see below for the
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// Memory(ea) <- Rd (Store) definition of ea.
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//
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// `S' determines whether the instruction is a Load (0) or a Store (1).
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// Loads appear in Rd one cycle after this instruction executes. If the
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// following instruction reads Rd, that instruction will be delayed by 1
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// clock cycle.
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//
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// PQ operation
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// -- ------------------------------------------
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// 00 ea = Rs1
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// 01 ea = Rs1, Rs1 <- Rs1 + constant
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// 10 ea = Rs1 + constant
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// 11 ea = Rs1 + constant, Rs1 <- Rs1 + constant
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//
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// The constant is sign-extended for this instruction.
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//
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// A Jump is accomplished by `Rd' being `pc', and it has *two* delay slots.
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class InstRM<bit S, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstLanai<outs, ins, asmstr, pattern> {
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bits<5> Rd;
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bits<5> Rs1;
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bit P;
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bit Q;
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bits<16> imm16;
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// Dummy variables to allow multiclass definition of RM and RRM
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bits<2> YL;
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bit E;
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let Opcode{3 - 1} = 0b100;
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let Opcode{0} = S;
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let Inst{27 - 23} = Rd;
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let Inst{22 - 18} = Rs1;
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let Inst{17} = P;
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let Inst{16} = Q;
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let Inst{15 - 0} = imm16;
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let PostEncoderMethod = "adjustPqBitsRmAndRrm";
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}
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//------------------------------------------------------------------------------
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// Register Register Memory (RRM)
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//------------------------------------------------------------------------------
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// Encoding:
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// -----------------------------------------------------------------
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// |1.0.1.S| . . . . | . . . . |P.Q| . . . . |B.B.B|J.J.J.J.J|Y.L.E|
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// -----------------------------------------------------------------
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// opcode Rd Rs1 Rs2 \ operation /
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//
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// Action:
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// Rd <- Memory(ea) (Load) see below for the
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// Memory(ea) <- Rd (Store) definition of ea.
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//
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// The RRM instruction is identical to the RM (*note RM::.) instruction
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// except that:
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//
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// 1. `Rs1 + constant' is replaced with `Rs1 op Rs2', where `op' is
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// determined in the same way as in the RR instruction (*note RR::.)
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// and
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//
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// 2. part-word memory accesses are allowed as specified below.
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//
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// If `BBB' != 111 (i.e.: For all but shift operations):
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// If `YLE' = 01- => fuLl-word memory access
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// If `YLE' = 00- => half-word memory access
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// If `YLE' = 10- => bYte memory access
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// If `YLE' = --1 => loads are zEro extended
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// If `YLE' = --0 => loads are sign extended
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//
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// If `BBB' = 111 (For shift operations):
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// fullword memory access are performed.
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//
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// All part-word loads write the least significant part of the
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// destination register with the higher-order bits zero- or sign-extended.
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// All part-word stores store the least significant part-word of the
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// source register in the destination memory location.
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//
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// A Jump is accomplished by `Rd' being `pc', and it has *two* delay slots.
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class InstRRM<bit S, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: InstLanai<outs, ins, asmstr, pattern> {
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bits<5> Rd;
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bits<5> Rs1;
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bits<5> Rs2;
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bit P;
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bit Q;
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bits<3> BBB;
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bits<5> JJJJJ;
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bits<2> YL;
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bit E;
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let Opcode{3 - 1} = 0b101;
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let Opcode{0} = S;
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let Inst{27 - 23} = Rd;
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let Inst{22 - 18} = Rs1;
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let Inst{17} = P;
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let Inst{16} = Q;
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let Inst{15 - 11} = Rs2;
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let Inst{10 - 8} = BBB;
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let Inst{7 - 3} = JJJJJ;
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let Inst{2 - 1} = YL;
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let Inst{0} = E;
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let PostEncoderMethod = "adjustPqBitsRmAndRrm";
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}
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//------------------------------------------------------------------------------
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// Conditional Branch (BR)
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//------------------------------------------------------------------------------
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// Encoding:
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// -----------------------------------------------------------------
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// |1.1.1.0|D.D.D| . . . . . . . . . . . . . . . . . . . . . . |0.I|
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// -----------------------------------------------------------------
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// opcode condition constant (23)
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//
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// Action:
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// if (condition) { `pc' <- 4*(zero-extended constant) }
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//
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// The BR instruction is an absolute branch.
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// The constant is scaled as shown by its position in the instruction word such
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// that it specifies word-aligned addresses in the range [0,2^25-4]
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//
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// The `DDDI' field selects the condition that causes the branch to be taken.
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// (the `I' (Invert sense) bit inverts the sense of the condition):
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//
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// DDDI logical function [code, used for...]
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// ---- -------------------------------------- ------------------------
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// 0000 1 [T, true]
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// 0001 0 [F, false]
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// 0010 C AND Z' [HI, high]
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// 0011 C' OR Z [LS, low or same]
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// 0100 C' [CC, carry cleared]
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// 0101 C [CS, carry set]
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// 0110 Z' [NE, not equal]
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// 0111 Z [EQ, equal]
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// 1000 V' [VC, oVerflow cleared]
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// 1001 V [VS, oVerflow set]
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// 1010 N' [PL, plus]
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// 1011 N [MI, minus]
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// 1100 (N AND V) OR (N' AND V') [GE, greater than or equal]
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// 1101 (N AND V') OR (N' AND V) [LT, less than]
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// 1110 (N AND V AND Z') OR (N' AND V' AND Z') [GT, greater than]
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// 1111 (Z) OR (N AND V') OR (N' AND V) [LE, less than or equal]
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//
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// If the branch is not taken, the BR instruction is a no-op. If the branch is
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// taken, the processor starts executing instructions at the branch target
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// address *after* the processor has executed one more instruction. That is,
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// the branch has one “branch delay slot”. Be very careful if you find yourself
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// wanting to put a branch in a branch delays slot!
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class InstBR<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstLanai<outs, ins, asmstr, pattern> {
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let Itinerary = IIC_ALU;
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bits<25> addr;
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bits<4> DDDI;
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let Opcode = 0b1110;
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let Inst{27 - 25} = DDDI{3 - 1};
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let Inst{24 - 0} = addr;
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// These instructions overwrite the last two address bits (which are assumed
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// and ensured to be 0).
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let Inst{1} = 0;
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let Inst{0} = DDDI{0};
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}
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//------------------------------------------------------------------------------
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// Conditional Branch Relative (BRR)
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//------------------------------------------------------------------------------
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// Encoding:
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// -----------------------------------------------------------------
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// |1.1.1.0|D.D.D|1|-| . . . . |-.-| . . . . . . . . . . . . . |1.I|
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// -----------------------------------------------------------------
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// opcode condition Rs1 constant (14)
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// Action:
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// if (condition) { ‘pc’ <- Rs1 + 4*sign-extended constant) }
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//
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// BRR behaves like BR, except the branch target address is a 16-bit PC relative
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// offset.
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class InstBRR<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstLanai<outs, ins, asmstr, pattern> {
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bits<4> DDDI;
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bits<5> Rs1;
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bits<16> imm16;
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let Opcode = 0b1110;
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let Inst{27 - 25} = DDDI{3 - 1};
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let Inst{24} = 1;
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let Inst{22 - 18} = Rs1;
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let Inst{17 - 16} = 0;
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let Inst{15 - 0} = imm16;
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// Overwrite last two bits which have to be zero
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let Inst{1} = 1;
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let Inst{0} = DDDI{0};
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// Set don't cares to zero
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let Inst{23} = 0;
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}
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//------------------------------------------------------------------------------
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// Conditional Set (SCC)
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//------------------------------------------------------------------------------
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// Encoding:
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// -----------------------------------------------------------------
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// |1.1.1.0|D.D.D|0.-| . . . . |-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-|1.I|
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// -----------------------------------------------------------------
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// opcode condition Rs1
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//
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// Action:
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// Rs1 <- logical function result
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//
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// SCC sets dst_reg to the boolean result of computing the logical function
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// specified by DDDI, as described in the table for the BR instruction.
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class InstSCC<dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: InstLanai<outs, ins, asmstr, pattern> {
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let Itinerary = IIC_ALU;
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bits<5> Rs1; // dst_reg in documentation
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bits<4> DDDI;
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let Opcode = 0b1110;
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let Inst{27 - 25} = DDDI{3 - 1};
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let Inst{24} = 0;
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let Inst{22 - 18} = Rs1;
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let Inst{1} = 1;
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let Inst{0} = DDDI{0};
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// Set don't cares to zero
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let Inst{23} = 0;
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let Inst{17 - 2} = 0;
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}
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//------------------------------------------------------------------------------
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// Special Load/Store (SLS)
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//------------------------------------------------------------------------------
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//
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// Encoding:
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// -----------------------------------------------------------------
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// |1.1.1.1| . . . . | . . . . |0.S| . . . . . . . . . . . . . . . |
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// -----------------------------------------------------------------
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// opcode Rd addr 5msb's address 16 lsb's
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//
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// Action:
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// If S = 0 (LOAD): Rd <- Memory(address);
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// If S = 1 (STORE): Memory(address) <- Rd
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//
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// The timing is the same as for RM (*note RM::.) and RRM (*note
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// RRM::.) instructions. The two low-order bits of the 21-bit address are
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// ignored. The address is zero extended. Fullword memory accesses are
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// performed.
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class InstSLS<bit S, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstLanai<outs, ins, asmstr, pattern> {
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bits<5> Rd;
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bits<5> msb;
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bits<16> lsb;
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let Opcode = 0b1111;
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let Inst{27 - 23} = Rd;
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let Inst{22 - 18} = msb;
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let Inst{17} = 0;
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let Inst{16} = S;
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let Inst{15 - 0} = lsb;
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}
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//------------------------------------------------------------------------------
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// Special Load Immediate (SLI)
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//------------------------------------------------------------------------------
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// Encoding:
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// -----------------------------------------------------------------
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// |1.1.1.1| . . . . | . . . . |1.0| . . . . . . . . . . . . . . . |
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// -----------------------------------------------------------------
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// opcode Rd const 5msb's constant 16 lsb's
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//
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// Action:
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// Rd <- constant
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//
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// The 21-bit constant is zero-extended. The timing is the same as the
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// RM instruction (*note RM::.).
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class InstSLI<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstLanai<outs, ins, asmstr, pattern> {
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bits<5> Rd;
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bits<5> msb;
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bits<16> lsb;
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let Opcode = 0b1111;
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let Inst{27 - 23} = Rd;
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let Inst{22 - 18} = msb;
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let Inst{17} = 1;
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let Inst{16} = 0;
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let Inst{15 - 0} = lsb;
|
||
}
|
||
|
||
//------------------------------------------------------------------------------
|
||
// Special Part-Word Load/Store (SPLS)
|
||
//------------------------------------------------------------------------------
|
||
// Encoding:
|
||
// -----------------------------------------------------------------
|
||
// |1.1.1.1| . . . . | . . . . |1.1.0.Y.S.E.P.Q| . . . . . . . . . |
|
||
// -----------------------------------------------------------------
|
||
// opcode Rd Rs1 constant (10)
|
||
//
|
||
// Action:
|
||
// If `YS' = 11 (bYte Store):
|
||
// Memory(ea) <- (least significant byte of Rr)
|
||
// If `YS' = 01 (halfword Store):
|
||
// Memory(ea) <- (least significant half-word of Rr)
|
||
// If `YS' = 10 (bYte load): Rr <- Memory(ea)
|
||
// If `YS' = 00 (halfword load): Rr <- Memory(ea)
|
||
// [Note: here ea is determined as in the RM instruction. ]
|
||
// If `SE' = 01 then the value is zEro extended
|
||
// before being loaded into Rd.
|
||
// If `SE' = 00 then the value is sign extended
|
||
// before being loaded into Rd.
|
||
//
|
||
// `P' and `Q' are used to determine `ea' as in the RM instruction. The
|
||
// constant is sign extended. The timing is the same as the RM and RRM
|
||
// instructions. *Note RM:: and *Note RRM::.
|
||
//
|
||
// All part-word loads write the part-word into the least significant
|
||
// part of the destination register, with the higher-order bits zero- or
|
||
// sign-extended. All part-word stores store the least significant
|
||
// part-word of the source register into the destination memory location.
|
||
class InstSPLS<dag outs, dag ins, string asmstr,
|
||
list<dag> pattern>
|
||
: InstLanai<outs, ins, asmstr, pattern> {
|
||
bits<5> Rd;
|
||
bits<5> Rs1;
|
||
bits<5> msb;
|
||
bit Y;
|
||
bit S;
|
||
bit E;
|
||
bit P;
|
||
bit Q;
|
||
bits<10> imm10;
|
||
|
||
let Opcode = 0b1111;
|
||
let Inst{27 - 23} = Rd;
|
||
let Inst{22 - 18} = Rs1;
|
||
let Inst{17 - 15} = 0b110;
|
||
let Inst{14} = Y;
|
||
let Inst{13} = S;
|
||
let Inst{12} = E;
|
||
let Inst{11} = P;
|
||
let Inst{10} = Q;
|
||
let Inst{9 - 0} = imm10;
|
||
|
||
let PostEncoderMethod = "adjustPqBitsSpls";
|
||
}
|
||
|
||
//------------------------------------------------------------------------------
|
||
// Special instructions (popc, leadz, trailz)
|
||
//------------------------------------------------------------------------------
|
||
// Encoding:
|
||
// -----------------------------------------------------------------
|
||
// |1.1.0.1| Rd | Rs1 |F.-| . . . . | . . | . . . . | OP |
|
||
// -----------------------------------------------------------------
|
||
// opcode Rd Rs1
|
||
// Action:
|
||
// Rd <- Perform action encoded in OP on Rs1
|
||
// OP is one of:
|
||
// 0b001 POPC Population count;
|
||
// 0b010 LEADZ Count number of leading zeros;
|
||
// 0b011 TRAILZ Count number of trailing zeros;
|
||
class InstSpecial<bits<3> op, dag outs, dag ins, string asmstr,
|
||
list<dag> pattern> : InstLanai<outs, ins, asmstr,
|
||
pattern>, Sched<[WriteALU]> {
|
||
let Itinerary = IIC_ALU;
|
||
bit F;
|
||
bits<5> Rd;
|
||
bits<5> Rs1;
|
||
|
||
let Opcode = 0b1101;
|
||
let Inst{27 - 23} = Rd;
|
||
let Inst{22 - 18} = Rs1;
|
||
let Inst{17} = F;
|
||
let Inst{16 - 3} = 0;
|
||
let Inst{2 - 0} = op;
|
||
}
|
||
|
||
// Pseudo instructions
|
||
class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
||
: InstLanai<outs, ins, asmstr, pattern> {
|
||
let Inst{15 - 0} = 0;
|
||
let isPseudo = 1;
|
||
}
|