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2f935bc924
Summary: This commit enables some of the arithmetic instructions for Nios2 ISA (for both R1 and R2 revisions), implements facilities required to emit those instructions and provides LIT tests for added instructions. Reviewed By: hfinkel Differential Revision: https://reviews.llvm.org/D41236 Author: belickim <mateusz.belicki@intel.com> llvm-svn: 322069
50 lines
1.5 KiB
C++
50 lines
1.5 KiB
C++
//===-- Nios2InstrInfo.h - Nios2 Instruction Information --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Nios2 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_NIOS2_NIOS2INSTRINFO_H
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#define LLVM_LIB_TARGET_NIOS2_NIOS2INSTRINFO_H
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#include "Nios2RegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "Nios2GenInstrInfo.inc"
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namespace llvm {
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class Nios2Subtarget;
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class Nios2InstrInfo : public Nios2GenInstrInfo {
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const Nios2RegisterInfo RI;
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const Nios2Subtarget &Subtarget;
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virtual void anchor();
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public:
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explicit Nios2InstrInfo(Nios2Subtarget &ST);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const Nios2RegisterInfo &getRegisterInfo() const { return RI; };
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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};
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} // namespace llvm
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#endif
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