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https://github.com/RPCS3/llvm-mirror.git
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156 lines
5.9 KiB
LLVM
156 lines
5.9 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vsli8:
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;CHECK: vsli.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vsli16:
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;CHECK: vsli.16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vsli32:
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;CHECK: vsli.32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 31, i32 31 >)
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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;CHECK: vsli64:
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;CHECK: vsli.64
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <1 x i64>* %B
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%tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 63 >)
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ret <1 x i64> %tmp3
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}
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define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vsliQ8:
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;CHECK: vsli.8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vsliQ16:
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;CHECK: vsli.16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vsliQ32:
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;CHECK: vsli.32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK: vsliQ64:
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;CHECK: vsli.64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 63, i64 63 >)
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ret <2 x i64> %tmp3
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}
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define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vsri8:
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;CHECK: vsri.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vsri16:
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;CHECK: vsri.16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vsri32:
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;CHECK: vsri.32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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;CHECK: vsri64:
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;CHECK: vsri.64
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <1 x i64>* %B
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%tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 -64 >)
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ret <1 x i64> %tmp3
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}
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define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vsriQ8:
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;CHECK: vsri.8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vsriQ16:
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;CHECK: vsri.16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vsriQ32:
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;CHECK: vsri.32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vsriQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK: vsriQ64:
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;CHECK: vsri.64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
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ret <2 x i64> %tmp3
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}
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declare <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64>, <1 x i64>, <1 x i64>) nounwind readnone
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declare <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone
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