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llvm-mirror/test/CodeGen/Mips/mips64countleading.ll
Akira Hatanaka 0af792d12b Expand 64-bit CTLZ nodes if target architecture does not support it. Add test
case for DCLO and DCLZ.

llvm-svn: 147022
2011-12-21 00:20:27 +00:00

20 lines
421 B
LLVM

; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
define i64 @t1(i64 %X) nounwind readnone {
entry:
; CHECK: dclz
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
ret i64 %tmp1
}
declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
define i64 @t3(i64 %X) nounwind readnone {
entry:
; CHECK: dclo
%neg = xor i64 %X, -1
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
ret i64 %tmp1
}