Matt Arsenault 1595f1e4ce AMDGPU: Custom lower more vector operations ... This avoids stack usage. llvm-svn: 292846		2017-01-23 23:09:58 +00:00
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AArch64	[AArch64][GlobalISel] Legalize narrow scalar fp->int conversions.	2017-01-23 21:10:14 +00:00
AMDGPU	AMDGPU: Custom lower more vector operations	2017-01-23 23:09:58 +00:00
ARM	[ARM] Classification Improvements to ARM Sched-Models. NFCI.	2017-01-23 20:20:39 +00:00
AVR
BPF
Generic
Hexagon	Treat segment [B, E) as not overlapping block with boundaries [A, B)	2017-01-18 23:12:19 +00:00
Inputs
Lanai
Mips	Fix some broken CHECK lines.	2017-01-22 20:28:56 +00:00
MIR	[MIRParser] Allow generic register specification on operand.	2017-01-20 00:29:59 +00:00
MSP430
NVPTX	Fix some broken CHECK lines.	2017-01-22 20:28:56 +00:00
PowerPC	[APFloat] Switch from (PPCDoubleDoubleImpl, IEEEdouble) layout to (IEEEdouble, IEEEdouble)	2017-01-23 22:39:35 +00:00
SPARC
SystemZ
Thumb
Thumb2
WebAssembly	[WebAssembly] Don't create bitcast-wrappers for varargs.	2017-01-20 20:50:29 +00:00
WinEH
X86	[X86][SSE] Add missing X86ISD::ANDNP combines.	2017-01-22 22:45:23 +00:00
XCore