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3262b6a145
xorl + setcc is generally the preferred sequence due to the partial register stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller. This fixes PR28146. The original commit tried inserting an 8bit-subreg into a GR32 (not GR32_ABCD) which was not appreciated by fast regalloc on 32-bit. llvm-svn: 274802
36 lines
1.0 KiB
LLVM
36 lines
1.0 KiB
LLVM
; RUN: llc --show-mc-encoding < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin10.0.0"
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declare i32 @foo();
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define i32 @f0(i32* nocapture %x) nounwind readonly ssp {
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entry:
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%tmp1 = call i32 @foo()
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; CHECK: cmpl $16777216, %eax
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; CHECK: # encoding: [0x3d,0x00,0x00,0x00,0x01]
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%cmp = icmp eq i32 %tmp1, 16777216 ; <i1> [#uses=1]
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%conv = zext i1 %cmp to i32 ; <i32> [#uses=1]
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ret i32 %conv
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}
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define i32 @f1() nounwind {
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%ax = tail call i16 asm sideeffect "", "={ax},~{dirflag},~{fpsr},~{flags}"()
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%conv = sext i16 %ax to i32
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ret i32 %conv
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; CHECK-LABEL: f1:
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; CHECK: cwtl ## encoding: [0x98]
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}
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define i64 @f2() nounwind {
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%eax = tail call i32 asm sideeffect "", "={ax},~{dirflag},~{fpsr},~{flags}"()
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%conv = sext i32 %eax to i64
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ret i64 %conv
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; CHECK-LABEL: f2:
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; CHECK: cltq ## encoding: [0x48,0x98]
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}
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