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fdf7e5830b
Structure the definitions a bit more like the other classes. The main change here is to split EXP with the done bit set to a separate opcode, so we can set mayLoad = 1 so that it won't be reordered before the other exp stores, since this has the special constraint that if the done bit is set then this should be the last exp in she shader. Previously all exp instructions were inferred to have unmodeled side effects. llvm-svn: 288695
210 lines
7.8 KiB
TableGen
210 lines
7.8 KiB
TableGen
//===-- SIIntrinsics.td - SI Intrinsic defs ----------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Backend internal SI Intrinsic Definitions. User code should not
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// directly use these.
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//
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "SI", isTarget = 1 in {
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def int_SI_packf16 : Intrinsic <[llvm_i32_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_SI_export : Intrinsic <[],
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[llvm_i32_ty, // en
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llvm_i32_ty, // vm (FIXME: should be i1)
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llvm_i32_ty, // done (FIXME: should be i1)
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llvm_i32_ty, // tgt
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llvm_i32_ty, // compr (FIXME: should be i1)
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llvm_float_ty, // src0
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llvm_float_ty, // src1
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llvm_float_ty, // src2
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llvm_float_ty], // src3
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[]
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>;
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def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_anyint_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]> ;
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// Fully-flexible TBUFFER_STORE_FORMAT_* except for the ADDR64 bit, which is not exposed
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def int_SI_tbuffer_store : Intrinsic <
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[],
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[llvm_anyint_ty, // rsrc(SGPR)
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llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32
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llvm_i32_ty, // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW
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llvm_i32_ty, // vaddr(VGPR)
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llvm_i32_ty, // soffset(SGPR)
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llvm_i32_ty, // inst_offset(imm)
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llvm_i32_ty, // dfmt(imm)
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llvm_i32_ty, // nfmt(imm)
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llvm_i32_ty, // offen(imm)
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llvm_i32_ty, // idxen(imm)
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llvm_i32_ty, // glc(imm)
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llvm_i32_ty, // slc(imm)
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llvm_i32_ty], // tfe(imm)
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[]>;
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// Fully-flexible BUFFER_LOAD_DWORD_* except for the ADDR64 bit, which is not exposed
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def int_SI_buffer_load_dword : Intrinsic <
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[llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32
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[llvm_anyint_ty, // rsrc(SGPR)
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llvm_anyint_ty, // vaddr(VGPR)
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llvm_i32_ty, // soffset(SGPR)
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llvm_i32_ty, // inst_offset(imm)
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llvm_i32_ty, // offen(imm)
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llvm_i32_ty, // idxen(imm)
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llvm_i32_ty, // glc(imm)
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llvm_i32_ty, // slc(imm)
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llvm_i32_ty], // tfe(imm)
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[IntrReadMem, IntrArgMemOnly]>;
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def int_SI_sendmsg : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], []>;
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// Fully-flexible SAMPLE instruction.
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class SampleRaw : Intrinsic <
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[llvm_v4f32_ty], // vdata(VGPR)
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[llvm_anyint_ty, // vaddr(VGPR)
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llvm_v8i32_ty, // rsrc(SGPR)
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llvm_v4i32_ty, // sampler(SGPR)
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llvm_i32_ty, // dmask(imm)
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llvm_i32_ty, // unorm(imm)
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llvm_i32_ty, // r128(imm)
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llvm_i32_ty, // da(imm)
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llvm_i32_ty, // glc(imm)
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llvm_i32_ty, // slc(imm)
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llvm_i32_ty, // tfe(imm)
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llvm_i32_ty], // lwe(imm)
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[IntrNoMem]>;
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// Image instruction without a sampler.
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class Image : Intrinsic <
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[llvm_v4f32_ty], // vdata(VGPR)
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[llvm_anyint_ty, // vaddr(VGPR)
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llvm_v8i32_ty, // rsrc(SGPR)
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llvm_i32_ty, // dmask(imm)
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llvm_i32_ty, // unorm(imm)
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llvm_i32_ty, // r128(imm)
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llvm_i32_ty, // da(imm)
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llvm_i32_ty, // glc(imm)
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llvm_i32_ty, // slc(imm)
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llvm_i32_ty, // tfe(imm)
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llvm_i32_ty], // lwe(imm)
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[IntrNoMem]>;
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// Basic sample
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def int_SI_image_sample : SampleRaw;
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def int_SI_image_sample_cl : SampleRaw;
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def int_SI_image_sample_d : SampleRaw;
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def int_SI_image_sample_d_cl : SampleRaw;
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def int_SI_image_sample_l : SampleRaw;
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def int_SI_image_sample_b : SampleRaw;
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def int_SI_image_sample_b_cl : SampleRaw;
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def int_SI_image_sample_lz : SampleRaw;
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def int_SI_image_sample_cd : SampleRaw;
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def int_SI_image_sample_cd_cl : SampleRaw;
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// Sample with comparison
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def int_SI_image_sample_c : SampleRaw;
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def int_SI_image_sample_c_cl : SampleRaw;
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def int_SI_image_sample_c_d : SampleRaw;
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def int_SI_image_sample_c_d_cl : SampleRaw;
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def int_SI_image_sample_c_l : SampleRaw;
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def int_SI_image_sample_c_b : SampleRaw;
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def int_SI_image_sample_c_b_cl : SampleRaw;
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def int_SI_image_sample_c_lz : SampleRaw;
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def int_SI_image_sample_c_cd : SampleRaw;
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def int_SI_image_sample_c_cd_cl : SampleRaw;
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// Sample with offsets
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def int_SI_image_sample_o : SampleRaw;
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def int_SI_image_sample_cl_o : SampleRaw;
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def int_SI_image_sample_d_o : SampleRaw;
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def int_SI_image_sample_d_cl_o : SampleRaw;
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def int_SI_image_sample_l_o : SampleRaw;
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def int_SI_image_sample_b_o : SampleRaw;
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def int_SI_image_sample_b_cl_o : SampleRaw;
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def int_SI_image_sample_lz_o : SampleRaw;
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def int_SI_image_sample_cd_o : SampleRaw;
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def int_SI_image_sample_cd_cl_o : SampleRaw;
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// Sample with comparison and offsets
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def int_SI_image_sample_c_o : SampleRaw;
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def int_SI_image_sample_c_cl_o : SampleRaw;
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def int_SI_image_sample_c_d_o : SampleRaw;
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def int_SI_image_sample_c_d_cl_o : SampleRaw;
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def int_SI_image_sample_c_l_o : SampleRaw;
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def int_SI_image_sample_c_b_o : SampleRaw;
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def int_SI_image_sample_c_b_cl_o : SampleRaw;
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def int_SI_image_sample_c_lz_o : SampleRaw;
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def int_SI_image_sample_c_cd_o : SampleRaw;
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def int_SI_image_sample_c_cd_cl_o : SampleRaw;
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// Basic gather4
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def int_SI_gather4 : SampleRaw;
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def int_SI_gather4_cl : SampleRaw;
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def int_SI_gather4_l : SampleRaw;
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def int_SI_gather4_b : SampleRaw;
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def int_SI_gather4_b_cl : SampleRaw;
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def int_SI_gather4_lz : SampleRaw;
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// Gather4 with comparison
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def int_SI_gather4_c : SampleRaw;
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def int_SI_gather4_c_cl : SampleRaw;
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def int_SI_gather4_c_l : SampleRaw;
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def int_SI_gather4_c_b : SampleRaw;
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def int_SI_gather4_c_b_cl : SampleRaw;
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def int_SI_gather4_c_lz : SampleRaw;
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// Gather4 with offsets
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def int_SI_gather4_o : SampleRaw;
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def int_SI_gather4_cl_o : SampleRaw;
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def int_SI_gather4_l_o : SampleRaw;
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def int_SI_gather4_b_o : SampleRaw;
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def int_SI_gather4_b_cl_o : SampleRaw;
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def int_SI_gather4_lz_o : SampleRaw;
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// Gather4 with comparison and offsets
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def int_SI_gather4_c_o : SampleRaw;
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def int_SI_gather4_c_cl_o : SampleRaw;
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def int_SI_gather4_c_l_o : SampleRaw;
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def int_SI_gather4_c_b_o : SampleRaw;
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def int_SI_gather4_c_b_cl_o : SampleRaw;
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def int_SI_gather4_c_lz_o : SampleRaw;
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def int_SI_getlod : SampleRaw;
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// Image instrinsics.
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def int_SI_image_load : Image;
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def int_SI_image_load_mip : Image;
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def int_SI_getresinfo : Image;
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/* Interpolation Intrinsics */
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def int_SI_fs_constant : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_SI_fs_interp : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_v2i32_ty], [IntrNoMem]>;
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} // End TargetPrefix = "SI", isTarget = 1
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let TargetPrefix = "amdgcn", isTarget = 1 in {
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// Emit 2.5 ulp, no denormal division. Should only be inserted by
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// pass based on !fpmath metadata.
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def int_amdgcn_fdiv_fast : Intrinsic<
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[llvm_float_ty], [llvm_float_ty], [IntrNoMem]
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>;
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/* Control flow Intrinsics */
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def int_amdgcn_if : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_empty_ty], [IntrConvergent]>;
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def int_amdgcn_else : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_empty_ty], [IntrConvergent]>;
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def int_amdgcn_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem, IntrConvergent]>;
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def int_amdgcn_if_break : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_i64_ty], [IntrNoMem, IntrConvergent]>;
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def int_amdgcn_else_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem, IntrConvergent]>;
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def int_amdgcn_loop : Intrinsic<[], [llvm_i64_ty, llvm_empty_ty], [IntrConvergent]>;
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def int_amdgcn_end_cf : Intrinsic<[], [llvm_i64_ty], [IntrConvergent]>;
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}
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