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I have added a new file: llvm/test/CodeGen/AArch64/README that describes what to do in the event one of the SVE codegen tests fails the warnings check. In addition, I've added comments to all the relevant SVE tests pointing users at the README file. Differential Revision: https://reviews.llvm.org/D83467
204 lines
7.9 KiB
LLVM
204 lines
7.9 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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;
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; ST1B
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;
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define void @st1b_i8(<vscale x 16 x i8> %data, <vscale x 16 x i1> %pred, i8* %a, i64 %index) {
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; CHECK-LABEL: st1b_i8:
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; CHECK: st1b { z0.b }, p0, [x0, x1]
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; CHECK-NEXT: ret
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%base = getelementptr i8, i8* %a, i64 %index
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call void @llvm.aarch64.sve.st1.nxv16i8(<vscale x 16 x i8> %data,
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<vscale x 16 x i1> %pred,
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i8* %base)
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ret void
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}
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define void @st1b_h(<vscale x 8 x i16> %data, <vscale x 8 x i1> %pred, i8* %a, i64 %index) {
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; CHECK-LABEL: st1b_h:
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; CHECK: st1b { z0.h }, p0, [x0, x1]
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; CHECK-NEXT: ret
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%base = getelementptr i8, i8* %a, i64 %index
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%trunc = trunc <vscale x 8 x i16> %data to <vscale x 8 x i8>
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call void @llvm.aarch64.sve.st1.nxv8i8(<vscale x 8 x i8> %trunc,
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<vscale x 8 x i1> %pred,
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i8* %base)
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ret void
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}
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define void @st1b_s(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pred, i8* %a, i64 %index) {
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; CHECK-LABEL: st1b_s:
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; CHECK: st1b { z0.s }, p0, [x0, x1]
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; CHECK-NEXT: ret
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%base = getelementptr i8, i8* %a, i64 %index
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%trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i8>
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call void @llvm.aarch64.sve.st1.nxv4i8(<vscale x 4 x i8> %trunc,
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<vscale x 4 x i1> %pred,
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i8* %base)
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ret void
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}
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define void @st1b_d(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pred, i8* %a, i64 %index) {
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; CHECK-LABEL: st1b_d:
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; CHECK: st1b { z0.d }, p0, [x0, x1]
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; CHECK-NEXT: ret
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%base = getelementptr i8, i8* %a, i64 %index
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%trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i8>
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call void @llvm.aarch64.sve.st1.nxv2i8(<vscale x 2 x i8> %trunc,
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<vscale x 2 x i1> %pred,
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i8* %base)
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ret void
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}
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;
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; ST1H
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;
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define void @st1h_i16(<vscale x 8 x i16> %data, <vscale x 8 x i1> %pred, i16* %a, i64 %index) {
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; CHECK-LABEL: st1h_i16:
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; CHECK: st1h { z0.h }, p0, [x0, x1, lsl #1]
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; CHECK-NEXT: ret
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%base = getelementptr i16, i16* %a, i64 %index
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call void @llvm.aarch64.sve.st1.nxv8i16(<vscale x 8 x i16> %data,
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<vscale x 8 x i1> %pred,
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i16* %base)
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ret void
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}
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define void @st1h_f16(<vscale x 8 x half> %data, <vscale x 8 x i1> %pred, half* %a, i64 %index) {
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; CHECK-LABEL: st1h_f16:
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; CHECK: st1h { z0.h }, p0, [x0, x1, lsl #1]
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; CHECK-NEXT: ret
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%base = getelementptr half, half* %a, i64 %index
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call void @llvm.aarch64.sve.st1.nxv8f16(<vscale x 8 x half> %data,
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<vscale x 8 x i1> %pred,
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half* %base)
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ret void
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}
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define void @st1h_bf16(<vscale x 8 x bfloat> %data, <vscale x 8 x i1> %pred, bfloat* %a, i64 %index) #0 {
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; CHECK-LABEL: st1h_bf16:
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; CHECK: st1h { z0.h }, p0, [x0, x1, lsl #1]
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; CHECK-NEXT: ret
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%base = getelementptr bfloat, bfloat* %a, i64 %index
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call void @llvm.aarch64.sve.st1.nxv8bf16(<vscale x 8 x bfloat> %data,
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<vscale x 8 x i1> %pred,
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bfloat* %base)
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ret void
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}
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define void @st1h_s(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pred, i16* %addr) {
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; CHECK-LABEL: st1h_s:
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; CHECK: st1h { z0.s }, p0, [x0]
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; CHECK-NEXT: ret
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%trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16>
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call void @llvm.aarch64.sve.st1.nxv4i16(<vscale x 4 x i16> %trunc,
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<vscale x 4 x i1> %pred,
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i16* %addr)
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ret void
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}
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define void @st1h_d(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pred, i16* %a, i64 %index) {
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; CHECK-LABEL: st1h_d:
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; CHECK: st1h { z0.d }, p0, [x0, x1, lsl #1]
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; CHECK-NEXT: ret
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%base = getelementptr i16, i16* %a, i64 %index
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%trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>
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call void @llvm.aarch64.sve.st1.nxv2i16(<vscale x 2 x i16> %trunc,
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<vscale x 2 x i1> %pred,
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i16* %base)
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ret void
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}
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;
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; ST1W
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;
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define void @st1w_i32(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pred, i32* %a, i64 %index) {
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; CHECK-LABEL: st1w_i32:
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; CHECK: st1w { z0.s }, p0, [x0, x1, lsl #2]
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; CHECK-NEXT: ret
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%base = getelementptr i32, i32* %a, i64 %index
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call void @llvm.aarch64.sve.st1.nxv4i32(<vscale x 4 x i32> %data,
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<vscale x 4 x i1> %pred,
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i32* %base)
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ret void
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}
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define void @st1w_f32(<vscale x 4 x float> %data, <vscale x 4 x i1> %pred, float* %a, i64 %index) {
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; CHECK-LABEL: st1w_f32:
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; CHECK: st1w { z0.s }, p0, [x0, x1, lsl #2]
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; CHECK-NEXT: ret
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%base = getelementptr float, float* %a, i64 %index
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call void @llvm.aarch64.sve.st1.nxv4f32(<vscale x 4 x float> %data,
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<vscale x 4 x i1> %pred,
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float* %base)
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ret void
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}
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define void @st1w_d(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pred, i32* %a, i64 %index) {
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; CHECK-LABEL: st1w_d:
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; CHECK: st1w { z0.d }, p0, [x0, x1, lsl #2]
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; CHECK-NEXT: ret
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%base = getelementptr i32, i32* %a, i64 %index
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%trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>
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call void @llvm.aarch64.sve.st1.nxv2i32(<vscale x 2 x i32> %trunc,
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<vscale x 2 x i1> %pred,
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i32* %base)
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ret void
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}
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;
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; ST1D
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;
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define void @st1d_i64(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pred, i64* %a, i64 %index) {
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; CHECK-LABEL: st1d_i64:
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; CHECK: st1d { z0.d }, p0, [x0, x1, lsl #3]
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; CHECK-NEXT: ret
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%base = getelementptr i64, i64* %a, i64 %index
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call void @llvm.aarch64.sve.st1.nxv2i64(<vscale x 2 x i64> %data,
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<vscale x 2 x i1> %pred,
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i64* %base)
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ret void
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}
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define void @st1d_f64(<vscale x 2 x double> %data, <vscale x 2 x i1> %pred, double* %a, i64 %index) {
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; CHECK-LABEL: st1d_f64:
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; CHECK: st1d { z0.d }, p0, [x0, x1, lsl #3]
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; CHECK-NEXT: ret
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%base = getelementptr double, double* %a, i64 %index
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call void @llvm.aarch64.sve.st1.nxv2f64(<vscale x 2 x double> %data,
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<vscale x 2 x i1> %pred,
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double* %base)
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ret void
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}
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declare void @llvm.aarch64.sve.st1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
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declare void @llvm.aarch64.sve.st1.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i1>, i8*)
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declare void @llvm.aarch64.sve.st1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
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declare void @llvm.aarch64.sve.st1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, half*)
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declare void @llvm.aarch64.sve.st1.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i1>, bfloat*)
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declare void @llvm.aarch64.sve.st1.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i1>, i8*)
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declare void @llvm.aarch64.sve.st1.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i1>, i16*)
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declare void @llvm.aarch64.sve.st1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
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declare void @llvm.aarch64.sve.st1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, float*)
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declare void @llvm.aarch64.sve.st1.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, i8*)
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declare void @llvm.aarch64.sve.st1.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i16*)
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declare void @llvm.aarch64.sve.st1.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32*)
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declare void @llvm.aarch64.sve.st1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i64*)
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declare void @llvm.aarch64.sve.st1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, double*)
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; +bf16 is required for the bfloat version.
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attributes #0 = { "target-features"="+sve,+bf16" }
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