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8495c2d57a
Followup to D73135. If the target doesn't have hard float (default for ARM), then we assert when trying to soften the result of vector reduction intrinsics. This patch marks these for expansion as well. (A bit odd to use vectors on a target without hard float ... but that's where you end up if you expose target-independent vector types.) Differential Revision: https://reviews.llvm.org/D73854
64 lines
2.2 KiB
LLVM
64 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-none-eabi -mattr=-neon | FileCheck %s --check-prefix=CHECK
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declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float, <4 x float>)
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declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v2f64(double, <2 x double>)
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declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128, <2 x fp128>)
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define float @test_v4f32(<4 x float> %a) nounwind {
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; CHECK-LABEL: test_v4f32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, r5, r6, lr}
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; CHECK-NEXT: push {r4, r5, r6, lr}
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; CHECK-NEXT: mov r5, r1
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; CHECK-NEXT: mov r1, r2
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; CHECK-NEXT: mov r4, r3
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; CHECK-NEXT: bl __aeabi_fadd
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; CHECK-NEXT: mov r6, r0
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; CHECK-NEXT: mov r0, r5
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; CHECK-NEXT: mov r1, r4
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; CHECK-NEXT: bl __aeabi_fadd
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; CHECK-NEXT: mov r1, r0
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; CHECK-NEXT: mov r0, r6
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; CHECK-NEXT: bl __aeabi_fadd
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; CHECK-NEXT: pop {r4, r5, r6, lr}
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; CHECK-NEXT: mov pc, lr
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%b = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float 0.0, <4 x float> %a)
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ret float %b
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}
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define double @test_v2f64(<2 x double> %a) nounwind {
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; CHECK-LABEL: test_v2f64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: bl __aeabi_dadd
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; CHECK-NEXT: pop {r11, lr}
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; CHECK-NEXT: mov pc, lr
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%b = call fast double @llvm.experimental.vector.reduce.v2.fadd.f64.v2f64(double zeroinitializer, <2 x double> %a)
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ret double %b
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}
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define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v2f128:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: ldr r12, [sp, #36]
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; CHECK-NEXT: str r12, [sp, #12]
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; CHECK-NEXT: ldr r12, [sp, #32]
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; CHECK-NEXT: str r12, [sp, #8]
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; CHECK-NEXT: ldr r12, [sp, #28]
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; CHECK-NEXT: str r12, [sp, #4]
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; CHECK-NEXT: ldr r12, [sp, #24]
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; CHECK-NEXT: str r12, [sp]
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; CHECK-NEXT: bl __addtf3
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: pop {r11, lr}
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; CHECK-NEXT: mov pc, lr
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%b = call fast fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a)
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ret fp128 %b
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}
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