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ca6d1aaf93
This patch cleans up and fixes issues in the M-Class system register handling: 1. It defines the system registers and the encoding (SYSm values) in one place: a new ARMSystemRegister.td using SearchableTable, thereby removing the hand-coded values which existed in multiple places. 2. Some system registers e.g. BASEPRI_MAX_NS which do not exist were being allowed! Ref: ARMv6/7/8M architecture reference manual. Reviewed by: @t.p.northover, @olist01, @john.brawn Differential Revision: https://reviews.llvm.org/D35209 llvm-svn: 308456
36 lines
1.0 KiB
Plaintext
36 lines
1.0 KiB
Plaintext
;===- ./lib/Target/ARM/LLVMBuild.txt ---------------------------*- Conf -*--===;
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;
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; The LLVM Compiler Infrastructure
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;
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; This file is distributed under the University of Illinois Open Source
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; License. See LICENSE.TXT for details.
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;
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;===------------------------------------------------------------------------===;
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;
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; This is an LLVMBuild description file for the components in this subdirectory.
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;
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; For more information on the LLVMBuild system, please see:
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;
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; http://llvm.org/docs/LLVMBuild.html
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;
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;===------------------------------------------------------------------------===;
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[common]
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subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo Utils
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[component_0]
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type = TargetGroup
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name = ARM
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parent = Target
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has_asmparser = 1
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has_asmprinter = 1
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has_disassembler = 1
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has_jit = 1
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[component_1]
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type = Library
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name = ARMCodeGen
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parent = ARM
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required_libraries = ARMAsmPrinter ARMDesc ARMInfo Analysis AsmPrinter CodeGen Core MC Scalar SelectionDAG Support Target GlobalISel ARMUtils
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add_to_library_groups = ARM
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