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19 lines
592 B
TableGen
19 lines
592 B
TableGen
//=- AMDGPURegisterBank.td - Describe the AMDGPU Banks -------*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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def SGPRRegBank : RegisterBank<"SGPR",
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[SReg_32, SReg_64, SReg_128, SReg_256, SReg_512]
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>;
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def VGPRRegBank : RegisterBank<"VGPR",
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[VGPR_32, VReg_64, VReg_96, VReg_128, VReg_256, VReg_512]
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>;
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def SCCRegBank : RegisterBank <"SCC", [SCC_CLASS ]>;
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