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llvm-mirror/test/CodeGen/X86/avx2-vector-shifts.ll
Stephen Lin 3ae734a60c Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. 
This was done with the following sed invocation to catch label lines demarking function boundaries:
    sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll
which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct.

llvm-svn: 186258
2013-07-13 20:38:47 +00:00

248 lines
6.4 KiB
LLVM
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
; AVX2 Logical Shift Left
define <16 x i16> @test_sllw_1(<16 x i16> %InVec) {
entry:
%shl = shl <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
ret <16 x i16> %shl
}
; CHECK-LABEL: test_sllw_1:
; CHECK: vpsllw $0, %ymm0, %ymm0
; CHECK: ret
define <16 x i16> @test_sllw_2(<16 x i16> %InVec) {
entry:
%shl = shl <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
ret <16 x i16> %shl
}
; CHECK-LABEL: test_sllw_2:
; CHECK: vpaddw %ymm0, %ymm0, %ymm0
; CHECK: ret
define <16 x i16> @test_sllw_3(<16 x i16> %InVec) {
entry:
%shl = shl <16 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
ret <16 x i16> %shl
}
; CHECK-LABEL: test_sllw_3:
; CHECK: vxorps %ymm0, %ymm0, %ymm0
; CHECK: ret
define <8 x i32> @test_slld_1(<8 x i32> %InVec) {
entry:
%shl = shl <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x i32> %shl
}
; CHECK-LABEL: test_slld_1:
; CHECK: vpslld $0, %ymm0, %ymm0
; CHECK: ret
define <8 x i32> @test_slld_2(<8 x i32> %InVec) {
entry:
%shl = shl <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
ret <8 x i32> %shl
}
; CHECK-LABEL: test_slld_2:
; CHECK: vpaddd %ymm0, %ymm0, %ymm0
; CHECK: ret
define <8 x i32> @test_slld_3(<8 x i32> %InVec) {
entry:
%shl = shl <8 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
ret <8 x i32> %shl
}
; CHECK-LABEL: test_slld_3:
; CHECK: vxorps %ymm0, %ymm0, %ymm0
; CHECK: ret
define <4 x i64> @test_sllq_1(<4 x i64> %InVec) {
entry:
%shl = shl <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
ret <4 x i64> %shl
}
; CHECK-LABEL: test_sllq_1:
; CHECK: vpsllq $0, %ymm0, %ymm0
; CHECK: ret
define <4 x i64> @test_sllq_2(<4 x i64> %InVec) {
entry:
%shl = shl <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
ret <4 x i64> %shl
}
; CHECK-LABEL: test_sllq_2:
; CHECK: vpaddq %ymm0, %ymm0, %ymm0
; CHECK: ret
define <4 x i64> @test_sllq_3(<4 x i64> %InVec) {
entry:
%shl = shl <4 x i64> %InVec, <i64 64, i64 64, i64 64, i64 64>
ret <4 x i64> %shl
}
; CHECK-LABEL: test_sllq_3:
; CHECK: vxorps %ymm0, %ymm0, %ymm0
; CHECK: ret
; AVX2 Arithmetic Shift
define <16 x i16> @test_sraw_1(<16 x i16> %InVec) {
entry:
%shl = ashr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
ret <16 x i16> %shl
}
; CHECK-LABEL: test_sraw_1:
; CHECK: vpsraw $0, %ymm0, %ymm0
; CHECK: ret
define <16 x i16> @test_sraw_2(<16 x i16> %InVec) {
entry:
%shl = ashr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
ret <16 x i16> %shl
}
; CHECK-LABEL: test_sraw_2:
; CHECK: vpsraw $1, %ymm0, %ymm0
; CHECK: ret
define <16 x i16> @test_sraw_3(<16 x i16> %InVec) {
entry:
%shl = ashr <16 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
ret <16 x i16> %shl
}
; CHECK-LABEL: test_sraw_3:
; CHECK: vpsraw $16, %ymm0, %ymm0
; CHECK: ret
define <8 x i32> @test_srad_1(<8 x i32> %InVec) {
entry:
%shl = ashr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x i32> %shl
}
; CHECK-LABEL: test_srad_1:
; CHECK: vpsrad $0, %ymm0, %ymm0
; CHECK: ret
define <8 x i32> @test_srad_2(<8 x i32> %InVec) {
entry:
%shl = ashr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
ret <8 x i32> %shl
}
; CHECK-LABEL: test_srad_2:
; CHECK: vpsrad $1, %ymm0, %ymm0
; CHECK: ret
define <8 x i32> @test_srad_3(<8 x i32> %InVec) {
entry:
%shl = ashr <8 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
ret <8 x i32> %shl
}
; CHECK-LABEL: test_srad_3:
; CHECK: vpsrad $32, %ymm0, %ymm0
; CHECK: ret
; SSE Logical Shift Right
define <16 x i16> @test_srlw_1(<16 x i16> %InVec) {
entry:
%shl = lshr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
ret <16 x i16> %shl
}
; CHECK-LABEL: test_srlw_1:
; CHECK: vpsrlw $0, %ymm0, %ymm0
; CHECK: ret
define <16 x i16> @test_srlw_2(<16 x i16> %InVec) {
entry:
%shl = lshr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
ret <16 x i16> %shl
}
; CHECK-LABEL: test_srlw_2:
; CHECK: vpsrlw $1, %ymm0, %ymm0
; CHECK: ret
define <16 x i16> @test_srlw_3(<16 x i16> %InVec) {
entry:
%shl = lshr <16 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
ret <16 x i16> %shl
}
; CHECK-LABEL: test_srlw_3:
; CHECK: vxorps %ymm0, %ymm0, %ymm0
; CHECK: ret
define <8 x i32> @test_srld_1(<8 x i32> %InVec) {
entry:
%shl = lshr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x i32> %shl
}
; CHECK-LABEL: test_srld_1:
; CHECK: vpsrld $0, %ymm0, %ymm0
; CHECK: ret
define <8 x i32> @test_srld_2(<8 x i32> %InVec) {
entry:
%shl = lshr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
ret <8 x i32> %shl
}
; CHECK-LABEL: test_srld_2:
; CHECK: vpsrld $1, %ymm0, %ymm0
; CHECK: ret
define <8 x i32> @test_srld_3(<8 x i32> %InVec) {
entry:
%shl = lshr <8 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
ret <8 x i32> %shl
}
; CHECK-LABEL: test_srld_3:
; CHECK: vxorps %ymm0, %ymm0, %ymm0
; CHECK: ret
define <4 x i64> @test_srlq_1(<4 x i64> %InVec) {
entry:
%shl = lshr <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
ret <4 x i64> %shl
}
; CHECK-LABEL: test_srlq_1:
; CHECK: vpsrlq $0, %ymm0, %ymm0
; CHECK: ret
define <4 x i64> @test_srlq_2(<4 x i64> %InVec) {
entry:
%shl = lshr <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
ret <4 x i64> %shl
}
; CHECK-LABEL: test_srlq_2:
; CHECK: vpsrlq $1, %ymm0, %ymm0
; CHECK: ret
define <4 x i64> @test_srlq_3(<4 x i64> %InVec) {
entry:
%shl = lshr <4 x i64> %InVec, <i64 64, i64 64, i64 64, i64 64>
ret <4 x i64> %shl
}
; CHECK-LABEL: test_srlq_3:
; CHECK: vxorps %ymm0, %ymm0, %ymm0
; CHECK: ret
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