Brendon Cahoon 16a6bb6581 [AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX ... Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149		2021-06-28 09:06:44 -04:00
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llvm	[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX	2021-06-28 09:06:44 -04:00
llvm-c	[ORC][C-bindings] Add access to LLJIT IRTransformLayer, ThreadSafeModule utils.	2021-06-19 11:50:27 +10:00