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6db76aaf10
This is still a work in progress but most of the NEON instruction set is supported. llvm-svn: 73919
102 lines
2.6 KiB
LLVM
102 lines
2.6 KiB
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
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; RUN: grep vmov.i8 %t | count 2
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; RUN: grep vmov.i16 %t | count 4
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; RUN: grep vmov.i32 %t | count 12
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; RUN: grep vmov.i64 %t | count 2
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; Note: function names do not include "vmov" to allow simple grep for opcodes
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define <8 x i8> @v_movi8() nounwind {
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ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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}
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define <4 x i16> @v_movi16a() nounwind {
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ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
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}
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; 0x1000 = 4096
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define <4 x i16> @v_movi16b() nounwind {
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ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
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}
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define <2 x i32> @v_movi32a() nounwind {
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ret <2 x i32> < i32 32, i32 32 >
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}
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; 0x2000 = 8192
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define <2 x i32> @v_movi32b() nounwind {
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ret <2 x i32> < i32 8192, i32 8192 >
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}
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; 0x200000 = 2097152
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define <2 x i32> @v_movi32c() nounwind {
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ret <2 x i32> < i32 2097152, i32 2097152 >
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}
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; 0x20000000 = 536870912
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define <2 x i32> @v_movi32d() nounwind {
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ret <2 x i32> < i32 536870912, i32 536870912 >
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}
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; 0x20ff = 8447
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define <2 x i32> @v_movi32e() nounwind {
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ret <2 x i32> < i32 8447, i32 8447 >
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}
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; 0x20ffff = 2162687
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define <2 x i32> @v_movi32f() nounwind {
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ret <2 x i32> < i32 2162687, i32 2162687 >
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}
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; 0xff0000ff0000ffff = 18374687574888349695
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define <1 x i64> @v_movi64() nounwind {
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ret <1 x i64> < i64 18374687574888349695 >
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}
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define <16 x i8> @v_movQi8() nounwind {
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ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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}
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define <8 x i16> @v_movQi16a() nounwind {
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ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
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}
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; 0x1000 = 4096
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define <8 x i16> @v_movQi16b() nounwind {
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ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
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}
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define <4 x i32> @v_movQi32a() nounwind {
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ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
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}
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; 0x2000 = 8192
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define <4 x i32> @v_movQi32b() nounwind {
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ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
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}
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; 0x200000 = 2097152
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define <4 x i32> @v_movQi32c() nounwind {
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ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
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}
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; 0x20000000 = 536870912
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define <4 x i32> @v_movQi32d() nounwind {
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ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
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}
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; 0x20ff = 8447
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define <4 x i32> @v_movQi32e() nounwind {
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ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
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}
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; 0x20ffff = 2162687
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define <4 x i32> @v_movQi32f() nounwind {
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ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
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}
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; 0xff0000ff0000ffff = 18374687574888349695
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define <2 x i64> @v_movQi64() nounwind {
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ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
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}
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