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Although the register scavenger can often find a spare register, an emergency spill slot is needed to guarantee success. Reserve this slot in cases where the function is known to have a large stack (meaning the scavenger may be needed when forming stack addresses). llvm-svn: 322269
61 lines
2.1 KiB
C++
61 lines
2.1 KiB
C++
//===-- RISCVFrameLowering.h - Define frame lowering for RISCV -*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class implements RISCV-specific bits of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVFRAMELOWERING_H
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#define LLVM_LIB_TARGET_RISCV_RISCVFRAMELOWERING_H
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#include "llvm/CodeGen/TargetFrameLowering.h"
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namespace llvm {
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class RISCVSubtarget;
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class RISCVFrameLowering : public TargetFrameLowering {
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public:
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explicit RISCVFrameLowering(const RISCVSubtarget &STI)
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: TargetFrameLowering(StackGrowsDown,
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/*StackAlignment=*/16,
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/*LocalAreaOffset=*/0),
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STI(STI) {}
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void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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int getFrameIndexReference(const MachineFunction &MF, int FI,
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unsigned &FrameReg) const override;
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void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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RegScavenger *RS) const override;
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void processFunctionBeforeFrameFinalized(MachineFunction &MF,
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RegScavenger *RS) const override;
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bool hasFP(const MachineFunction &MF) const override;
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MachineBasicBlock::iterator
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override {
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return MBB.erase(MI);
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}
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protected:
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const RISCVSubtarget &STI;
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private:
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void determineFrameLayout(MachineFunction &MF) const;
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void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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int64_t Val, MachineInstr::MIFlag Flag) const;
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};
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}
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#endif
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