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84c8374521
Summary: Without the SrcVT its hard to know what is really being asked for. For example if your target has 128, 256, and 512 bit vectors. Maybe extracting 128 from 256 is cheap, but maybe extracting 128 from 512 is not. For x86 we do support extracting a quarter of a 512-bit register. But for i1 vectors we don't have isel patterns for extracting arbitrary pieces. So we need this to have a correct implementation of isExtractSubvectorCheap for mask vectors. Reviewers: RKSimon, zvi, efriedma Reviewed By: RKSimon Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D36649 llvm-svn: 310793
775 lines
33 KiB
C++
775 lines
33 KiB
C++
//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that ARM uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
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#define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
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#include "MCTargetDesc/ARMBaseInfo.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineValueType.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Target/TargetLowering.h"
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#include <utility>
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namespace llvm {
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class ARMSubtarget;
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class InstrItineraryData;
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namespace ARMISD {
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// ARM Specific DAG Nodes
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enum NodeType : unsigned {
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// Start the numbering where the builtin ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
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// TargetExternalSymbol, and TargetGlobalAddress.
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WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
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// PIC mode.
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WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
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// Add pseudo op to model memcpy for struct byval.
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COPY_STRUCT_BYVAL,
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CALL, // Function call.
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CALL_PRED, // Function call that's predicable.
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CALL_NOLINK, // Function call with branch not branch-and-link.
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BRCOND, // Conditional branch.
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BR_JT, // Jumptable branch.
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BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
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RET_FLAG, // Return with a flag operand.
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INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
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PIC_ADD, // Add with a PC operand and a PIC label.
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CMP, // ARM compare instructions.
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CMN, // ARM CMN instructions.
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CMPZ, // ARM compare that sets only Z flag.
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CMPFP, // ARM VFP compare instruction, sets FPSCR.
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CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
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FMSTAT, // ARM fmstat instruction.
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CMOV, // ARM conditional move instructions.
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SSAT, // Signed saturation
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BCC_i64,
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SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
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SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
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RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
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ADDC, // Add with carry
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ADDE, // Add using carry
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SUBC, // Sub with carry
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SUBE, // Sub using carry
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VMOVRRD, // double to two gprs.
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VMOVDRR, // Two gprs to double.
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EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
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EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
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EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
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TC_RETURN, // Tail call return pseudo.
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THREAD_POINTER,
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DYN_ALLOC, // Dynamic allocation on the stack.
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MEMBARRIER_MCR, // Memory barrier (MCR)
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PRELOAD, // Preload
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WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
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WIN__DBZCHK, // Windows' divide by zero check
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VCEQ, // Vector compare equal.
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VCEQZ, // Vector compare equal to zero.
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VCGE, // Vector compare greater than or equal.
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VCGEZ, // Vector compare greater than or equal to zero.
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VCLEZ, // Vector compare less than or equal to zero.
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VCGEU, // Vector compare unsigned greater than or equal.
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VCGT, // Vector compare greater than.
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VCGTZ, // Vector compare greater than zero.
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VCLTZ, // Vector compare less than zero.
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VCGTU, // Vector compare unsigned greater than.
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VTST, // Vector test bits.
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// Vector shift by immediate:
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VSHL, // ...left
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VSHRs, // ...right (signed)
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VSHRu, // ...right (unsigned)
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// Vector rounding shift by immediate:
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VRSHRs, // ...right (signed)
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VRSHRu, // ...right (unsigned)
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VRSHRN, // ...right narrow
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// Vector saturating shift by immediate:
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VQSHLs, // ...left (signed)
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VQSHLu, // ...left (unsigned)
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VQSHLsu, // ...left (signed to unsigned)
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VQSHRNs, // ...right narrow (signed)
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VQSHRNu, // ...right narrow (unsigned)
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VQSHRNsu, // ...right narrow (signed to unsigned)
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// Vector saturating rounding shift by immediate:
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VQRSHRNs, // ...right narrow (signed)
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VQRSHRNu, // ...right narrow (unsigned)
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VQRSHRNsu, // ...right narrow (signed to unsigned)
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// Vector shift and insert:
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VSLI, // ...left
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VSRI, // ...right
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// Vector get lane (VMOV scalar to ARM core register)
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// (These are used for 8- and 16-bit element types only.)
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VGETLANEu, // zero-extend vector extract element
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VGETLANEs, // sign-extend vector extract element
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// Vector move immediate and move negated immediate:
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VMOVIMM,
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VMVNIMM,
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// Vector move f32 immediate:
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VMOVFPIMM,
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// Vector duplicate:
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VDUP,
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VDUPLANE,
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// Vector shuffles:
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VEXT, // extract
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VREV64, // reverse elements within 64-bit doublewords
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VREV32, // reverse elements within 32-bit words
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VREV16, // reverse elements within 16-bit halfwords
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VZIP, // zip (interleave)
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VUZP, // unzip (deinterleave)
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VTRN, // transpose
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VTBL1, // 1-register shuffle with mask
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VTBL2, // 2-register shuffle with mask
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// Vector multiply long:
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VMULLs, // ...signed
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VMULLu, // ...unsigned
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SMULWB, // Signed multiply word by half word, bottom
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SMULWT, // Signed multiply word by half word, top
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UMLAL, // 64bit Unsigned Accumulate Multiply
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SMLAL, // 64bit Signed Accumulate Multiply
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UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
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SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
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SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
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SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
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SMLALTT, // 64-bit signed accumulate multiply top, top 16
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SMLALD, // Signed multiply accumulate long dual
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SMLALDX, // Signed multiply accumulate long dual exchange
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SMLSLD, // Signed multiply subtract long dual
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SMLSLDX, // Signed multiply subtract long dual exchange
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// Operands of the standard BUILD_VECTOR node are not legalized, which
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// is fine if BUILD_VECTORs are always lowered to shuffles or other
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// operations, but for ARM some BUILD_VECTORs are legal as-is and their
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// operands need to be legalized. Define an ARM-specific version of
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// BUILD_VECTOR for this purpose.
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BUILD_VECTOR,
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// Bit-field insert
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BFI,
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// Vector OR with immediate
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VORRIMM,
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// Vector AND with NOT of immediate
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VBICIMM,
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// Vector bitwise select
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VBSL,
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// Pseudo-instruction representing a memory copy using ldm/stm
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// instructions.
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MEMCPY,
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// Vector load N-element structure to all lanes:
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VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
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VLD2DUP,
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VLD3DUP,
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VLD4DUP,
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// NEON loads with post-increment base updates:
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VLD1_UPD,
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VLD2_UPD,
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VLD3_UPD,
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VLD4_UPD,
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VLD2LN_UPD,
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VLD3LN_UPD,
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VLD4LN_UPD,
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VLD1DUP_UPD,
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VLD2DUP_UPD,
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VLD3DUP_UPD,
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VLD4DUP_UPD,
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// NEON stores with post-increment base updates:
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VST1_UPD,
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VST2_UPD,
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VST3_UPD,
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VST4_UPD,
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VST2LN_UPD,
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VST3LN_UPD,
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VST4LN_UPD
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};
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} // end namespace ARMISD
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/// Define some predicates that are used for node matching.
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namespace ARM {
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bool isBitFieldInvertedMask(unsigned v);
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} // end namespace ARM
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//===--------------------------------------------------------------------===//
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// ARMTargetLowering - ARM Implementation of the TargetLowering interface
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class ARMTargetLowering : public TargetLowering {
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public:
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explicit ARMTargetLowering(const TargetMachine &TM,
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const ARMSubtarget &STI);
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unsigned getJumpTableEncoding() const override;
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bool useSoftFloat() const override;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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/// ReplaceNodeResults - Replace the results of node with an illegal result
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/// type with new values built out of custom code.
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///
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) const override;
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const char *getTargetNodeName(unsigned Opcode) const override;
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bool isSelectSupported(SelectSupportKind Kind) const override {
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// ARM does not support scalar condition selects on vectors.
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return (Kind != ScalarCondVectorVal);
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}
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/// getSetCCResultType - Return the value type to use for ISD::SETCC.
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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EVT VT) const override;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *MBB) const override;
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void AdjustInstrPostInstrSelection(MachineInstr &MI,
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SDNode *Node) const override;
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SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
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SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
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SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
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/// allowsMisalignedMemoryAccesses - Returns true if the target allows
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/// unaligned memory accesses of the specified type. Returns whether it
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/// is "fast" by reference in the second argument.
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
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unsigned Align,
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bool *Fast) const override;
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EVT getOptimalMemOpType(uint64_t Size,
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unsigned DstAlign, unsigned SrcAlign,
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bool IsMemset, bool ZeroMemset,
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bool MemcpyStrSrc,
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MachineFunction &MF) const override;
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using TargetLowering::isZExtFree;
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bool isZExtFree(SDValue Val, EVT VT2) const override;
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bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
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bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
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Type *Ty, unsigned AS,
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Instruction *I = nullptr) const override;
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/// getScalingFactorCost - Return the cost of the scaling used in
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/// addressing mode represented by AM.
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/// If the AM is supported, the return value must be >= 0.
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/// If the AM is not supported, the return value must be negative.
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int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS) const override;
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bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
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/// isLegalICmpImmediate - Return true if the specified immediate is legal
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/// icmp immediate, that is the target has icmp instructions which can
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/// compare a register against the immediate without having to materialize
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/// the immediate into a register.
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bool isLegalICmpImmediate(int64_t Imm) const override;
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/// isLegalAddImmediate - Return true if the specified immediate is legal
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/// add immediate, that is the target has add instructions which can
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/// add a register and the immediate without having to materialize
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/// the immediate into a register.
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bool isLegalAddImmediate(int64_t Imm) const override;
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/// getPreIndexedAddressParts - returns true by value, base pointer and
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/// offset pointer and addressing mode by reference if the node's address
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/// can be legally represented as pre-indexed load / store address.
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bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const override;
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/// getPostIndexedAddressParts - returns true by value, base pointer and
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/// offset pointer and addressing mode by reference if this node can be
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/// combined with a load / store to form a post-indexed load / store.
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bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
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SDValue &Offset, ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const override;
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void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
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const APInt &DemandedElts,
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const SelectionDAG &DAG,
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unsigned Depth) const override;
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bool ExpandInlineAsm(CallInst *CI) const override;
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ConstraintType getConstraintType(StringRef Constraint) const override;
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/// Examine constraint string and operand type and determine a weight value.
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/// The operand object must already have been set up with the operand type.
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ConstraintWeight getSingleConstraintMatchWeight(
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AsmOperandInfo &info, const char *constraint) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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const char *LowerXConstraint(EVT ConstraintVT) const override;
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
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/// true it means one of the asm constraint of the inline asm instruction
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/// being processed is 'm'.
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void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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unsigned
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getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
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if (ConstraintCode == "Q")
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return InlineAsm::Constraint_Q;
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else if (ConstraintCode == "o")
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return InlineAsm::Constraint_o;
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else if (ConstraintCode.size() == 2) {
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if (ConstraintCode[0] == 'U') {
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switch(ConstraintCode[1]) {
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default:
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break;
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case 'm':
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return InlineAsm::Constraint_Um;
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case 'n':
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return InlineAsm::Constraint_Un;
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case 'q':
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return InlineAsm::Constraint_Uq;
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case 's':
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return InlineAsm::Constraint_Us;
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case 't':
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return InlineAsm::Constraint_Ut;
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case 'v':
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return InlineAsm::Constraint_Uv;
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case 'y':
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return InlineAsm::Constraint_Uy;
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}
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}
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}
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return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
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}
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const ARMSubtarget* getSubtarget() const {
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return Subtarget;
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}
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/// getRegClassFor - Return the register class that should be used for the
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/// specified value type.
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const TargetRegisterClass *getRegClassFor(MVT VT) const override;
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/// Returns true if a cast between SrcAS and DestAS is a noop.
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bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
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// Addrspacecasts are always noops.
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return true;
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}
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bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
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unsigned &PrefAlign) const override;
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/// createFastISel - This method returns a target specific FastISel object,
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/// or null if the target does not support "fast" ISel.
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FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo) const override;
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Sched::Preference getSchedulingPreference(SDNode *N) const override;
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bool
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isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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/// isFPImmLegal - Returns true if the target can instruction select the
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/// specified FP immediate natively. If false, the legalizer will
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/// materialize the FP immediate as a load from a constant pool.
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bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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bool getTgtMemIntrinsic(IntrinsicInfo &Info,
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const CallInst &I,
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unsigned Intrinsic) const override;
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/// \brief Returns true if it is beneficial to convert a load of a constant
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/// to just the constant itself.
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bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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Type *Ty) const override;
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/// Return true if EXTRACT_SUBVECTOR is cheap for this result type
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/// with this index.
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bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
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unsigned Index) const override;
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/// \brief Returns true if an argument of type Ty needs to be passed in a
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/// contiguous block of registers in calling convention CallConv.
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bool functionArgumentNeedsConsecutiveRegisters(
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Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
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/// If a physical register, this returns the register that receives the
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/// exception address on entry to an EH pad.
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unsigned
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getExceptionPointerRegister(const Constant *PersonalityFn) const override;
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/// If a physical register, this returns the register that receives the
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/// exception typeid on entry to a landing pad.
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unsigned
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getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
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|
|
Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
|
|
Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
|
|
AtomicOrdering Ord) const override;
|
|
Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
|
|
Value *Addr, AtomicOrdering Ord) const override;
|
|
|
|
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
|
|
|
|
Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
|
|
AtomicOrdering Ord) const override;
|
|
Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
|
|
AtomicOrdering Ord) const override;
|
|
|
|
unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
|
|
|
|
bool lowerInterleavedLoad(LoadInst *LI,
|
|
ArrayRef<ShuffleVectorInst *> Shuffles,
|
|
ArrayRef<unsigned> Indices,
|
|
unsigned Factor) const override;
|
|
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
|
|
unsigned Factor) const override;
|
|
|
|
bool shouldInsertFencesForAtomic(const Instruction *I) const override;
|
|
TargetLoweringBase::AtomicExpansionKind
|
|
shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
|
|
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
|
|
TargetLoweringBase::AtomicExpansionKind
|
|
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
|
|
bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
|
|
|
|
bool useLoadStackGuardNode() const override;
|
|
|
|
bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
|
|
unsigned &Cost) const override;
|
|
|
|
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
|
|
const SelectionDAG &DAG) const override {
|
|
// Do not merge to larger than i32.
|
|
return (MemVT.getSizeInBits() <= 32);
|
|
}
|
|
|
|
bool isCheapToSpeculateCttz() const override;
|
|
bool isCheapToSpeculateCtlz() const override;
|
|
|
|
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
|
|
return VT.isScalarInteger();
|
|
}
|
|
|
|
bool supportSwiftError() const override {
|
|
return true;
|
|
}
|
|
|
|
bool hasStandaloneRem(EVT VT) const override {
|
|
return HasStandaloneRem;
|
|
}
|
|
|
|
CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
|
|
CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
|
|
|
|
/// Returns true if \p VecTy is a legal interleaved access type. This
|
|
/// function checks the vector element type and the overall width of the
|
|
/// vector.
|
|
bool isLegalInterleavedAccessType(VectorType *VecTy,
|
|
const DataLayout &DL) const;
|
|
|
|
/// Returns the number of interleaved accesses that will be generated when
|
|
/// lowering accesses of the given type.
|
|
unsigned getNumInterleavedAccesses(VectorType *VecTy,
|
|
const DataLayout &DL) const;
|
|
|
|
void finalizeLowering(MachineFunction &MF) const override;
|
|
|
|
protected:
|
|
std::pair<const TargetRegisterClass *, uint8_t>
|
|
findRepresentativeClass(const TargetRegisterInfo *TRI,
|
|
MVT VT) const override;
|
|
|
|
private:
|
|
/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
|
|
/// make the right decision when generating code for different targets.
|
|
const ARMSubtarget *Subtarget;
|
|
|
|
const TargetRegisterInfo *RegInfo;
|
|
|
|
const InstrItineraryData *Itins;
|
|
|
|
/// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
|
|
///
|
|
unsigned ARMPCLabelIndex;
|
|
|
|
// TODO: remove this, and have shouldInsertFencesForAtomic do the proper
|
|
// check.
|
|
bool InsertFencesForAtomic;
|
|
|
|
bool HasStandaloneRem = true;
|
|
|
|
void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
|
|
void addDRTypeForNEON(MVT VT);
|
|
void addQRTypeForNEON(MVT VT);
|
|
std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
|
|
|
|
typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
|
|
|
|
void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
|
|
SDValue &Arg, RegsToPassVector &RegsToPass,
|
|
CCValAssign &VA, CCValAssign &NextVA,
|
|
SDValue &StackPtr,
|
|
SmallVectorImpl<SDValue> &MemOpChains,
|
|
ISD::ArgFlagsTy Flags) const;
|
|
SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
|
|
SDValue &Root, SelectionDAG &DAG,
|
|
const SDLoc &dl) const;
|
|
|
|
CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
|
|
bool isVarArg) const;
|
|
CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
|
|
bool isVarArg) const;
|
|
SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
|
|
const SDLoc &dl, SelectionDAG &DAG,
|
|
const CCValAssign &VA,
|
|
ISD::ArgFlagsTy Flags) const;
|
|
SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
|
|
const ARMSubtarget *Subtarget) const;
|
|
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
|
|
SelectionDAG &DAG) const;
|
|
SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
|
|
SelectionDAG &DAG,
|
|
TLSModel::Model model) const;
|
|
SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
|
|
const ARMSubtarget *ST) const;
|
|
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
|
|
const ARMSubtarget *ST) const;
|
|
SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
|
|
void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
|
|
SmallVectorImpl<SDValue> &Results) const;
|
|
SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
|
|
SDValue &Chain) const;
|
|
SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
|
|
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
unsigned getRegisterByName(const char* RegName, EVT VT,
|
|
SelectionDAG &DAG) const override;
|
|
|
|
/// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
|
|
/// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
|
|
/// expanded to FMAs when this method returns true, otherwise fmuladd is
|
|
/// expanded to fmul + fadd.
|
|
///
|
|
/// ARM supports both fused and unfused multiply-add operations; we already
|
|
/// lower a pair of fmul and fadd to the latter so it's not clear that there
|
|
/// would be a gain or that the gain would be worthwhile enough to risk
|
|
/// correctness bugs.
|
|
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
|
|
|
|
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
const SDLoc &dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
|
|
SDValue ThisVal) const;
|
|
|
|
bool supportSplitCSR(MachineFunction *MF) const override {
|
|
return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
|
|
MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
|
|
}
|
|
|
|
void initializeSplitCSR(MachineBasicBlock *Entry) const override;
|
|
void insertCopiesSplitCSR(
|
|
MachineBasicBlock *Entry,
|
|
const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
|
|
|
|
SDValue
|
|
LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
const SDLoc &dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const override;
|
|
|
|
int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
|
|
SDValue &Chain, const Value *OrigArg,
|
|
unsigned InRegsParamRecordIdx, int ArgOffset,
|
|
unsigned ArgSize) const;
|
|
|
|
void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
|
|
const SDLoc &dl, SDValue &Chain,
|
|
unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
|
|
bool ForceMutable = false) const;
|
|
|
|
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|
SmallVectorImpl<SDValue> &InVals) const override;
|
|
|
|
/// HandleByVal - Target-specific cleanup for ByVal support.
|
|
void HandleByVal(CCState *, unsigned &, unsigned) const override;
|
|
|
|
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
|
|
/// for tail call optimization. Targets which want to do tail call
|
|
/// optimization should implement this function.
|
|
bool IsEligibleForTailCallOptimization(SDValue Callee,
|
|
CallingConv::ID CalleeCC,
|
|
bool isVarArg,
|
|
bool isCalleeStructRet,
|
|
bool isCallerStructRet,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SelectionDAG& DAG) const;
|
|
|
|
bool CanLowerReturn(CallingConv::ID CallConv,
|
|
MachineFunction &MF, bool isVarArg,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
LLVMContext &Context) const override;
|
|
|
|
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SDLoc &dl, SelectionDAG &DAG) const override;
|
|
|
|
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
|
|
|
|
bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
|
|
|
|
SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
|
|
SDValue ARMcc, SDValue CCR, SDValue Cmp,
|
|
SelectionDAG &DAG) const;
|
|
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
|
|
SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
|
|
SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
|
|
const SDLoc &dl, bool InvalidOnQNaN) const;
|
|
SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
|
|
|
|
SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
|
|
MachineBasicBlock *DispatchBB, int FI) const;
|
|
|
|
void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
|
|
|
|
bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
|
|
|
|
MachineBasicBlock *EmitStructByval(MachineInstr &MI,
|
|
MachineBasicBlock *MBB) const;
|
|
|
|
MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
|
|
MachineBasicBlock *MBB) const;
|
|
MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
|
|
MachineBasicBlock *MBB) const;
|
|
};
|
|
|
|
enum NEONModImmType {
|
|
VMOVModImm,
|
|
VMVNModImm,
|
|
OtherModImm
|
|
};
|
|
|
|
namespace ARM {
|
|
|
|
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
|
const TargetLibraryInfo *libInfo);
|
|
|
|
} // end namespace ARM
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
|