Simon Pilgrim 1787dc0460 [CostModel][X86] i8/i16 sitofp/uitofp are sext/zext to i32 for sitofp ... Provide a generic fallback that extends sub-i32 scalars before using the existing sitofp instructions. These numbers can be tweaked for specific sse levels, but we should get the default handling in place first. We get the extension for free for non-vector loads.		2021-07-06 13:58:52 +01:00
..
AArch64	[AArch64][CostModel] Add cost model for experimental.vector.splice	2021-07-05 14:30:24 +01:00
AMDGPU	[AMDGPU] PHI node cost should not be counted for the size and latency.	2021-06-30 16:11:17 +03:00
ARM	[InstructionCost] Don't conflate Invalid costs with Unknown costs.	2021-03-30 09:29:42 +01:00
PowerPC	[Cost]Canonicalize the cost for logical or/and reductions.	2021-03-19 11:01:58 -07:00
RISCV	[RISCV] Expand unaligned fixed-length vector memory accesses	2021-06-02 09:27:44 +01:00
SystemZ	Revert "[NFC] remove explicit default value for strboolattr attribute in tests"	2021-05-24 19:43:40 +02:00
X86	[CostModel][X86] i8/i16 sitofp/uitofp are sext/zext to i32 for sitofp	2021-07-06 13:58:52 +01:00
free-intrinsics-datalayout.ll	[noalias.decl] Look through llvm.experimental.noalias.scope.decl	2021-01-19 20:09:42 +01:00
free-intrinsics-no_info.ll	[noalias.decl] Look through llvm.experimental.noalias.scope.decl	2021-01-19 20:09:42 +01:00
no_info.ll