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852d642125
Summary: "ww" and "ws" are both constraint codes for VSX vector registers that hold scalar double data. "ww" is preferred for float while "ws" is preferred for double. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D64119 llvm-svn: 365106
50 lines
1.6 KiB
LLVM
50 lines
1.6 KiB
LLVM
; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
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define signext i32 @foo(<4 x float> %__A) {
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entry:
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%0 = tail call { i32, <4 x float> } asm "xxsldwi ${1:x},${2:x},${2:x},3;\0Axscvspdp ${1:x},${1:x};\0Afctiw $1,$1;\0Amfvsrd $0,${1:x};\0A", "=r,=&^wa,^wa"(<4 x float> %__A)
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%asmresult = extractvalue { i32, <4 x float> } %0, 0
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ret i32 %asmresult
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; CHECK-LABEL: foo:
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; CHECK: #APP
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; CHECK: xxsldwi vs0, v2, v2, 3
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; CHECK: xscvspdp f0, f0
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; CHECK: fctiw f0, f0
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; CHECK: mffprd r3, f0
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; CHECK: #NO_APP
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}
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define signext i32 @foo1(<4 x float> %__A) {
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entry:
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%0 = tail call { i32, <4 x float> } asm "xxsldwi ${1:x},${2:x},${2:x},3;\0Axscvspdp ${1:x},${1:x};\0Afctiw $1,$1;\0Amfvsrd $0,${1:x};\0A", "=r,=&^wi,^wa"(<4 x float> %__A)
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%asmresult = extractvalue { i32, <4 x float> } %0, 0
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ret i32 %asmresult
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; CHECK-LABEL: foo1:
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; CHECK: #APP
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; CHECK: xxsldwi vs0, v2, v2, 3
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; CHECK: xscvspdp f0, f0
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; CHECK: fctiw f0, f0
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; CHECK: mffprd r3, f0
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; CHECK: #NO_APP
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; CHECK: extsw r3, r3
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}
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define double @test() {
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entry:
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%0 = tail call double asm "mtvsrd ${0:x}, 1", "=^ws,~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14}"()
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ret double %0
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; CHECK-LABEL: test:
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; CHECK: #APP
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; CHECK: mtvsrd v2, r1
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; CHECK: #NO_APP
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}
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define float @test_ww(float %x, float %y) {
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%1 = tail call float asm "xsmaxdp ${0:x}, ${1:x}, ${2:x}", "=^ww,^ww,^ww"(float %x, float %y)
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ret float %1
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; CHECK-LABEL: test_ww:
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; CHECK: #APP
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; CHECK: xsmaxdp f1, f1, f2
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; CHECK: #NO_APP
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}
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