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https://github.com/RPCS3/llvm-mirror.git
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f6f0a5745d
We currently miss a number of opportunities to emit single-instruction VMRG[LH][BHW] instructions for shuffles on little endian subtargets. Although this in itself is not a huge performance opportunity since loading the permute vector for a VPERM can always be pulled out of loops, producing such merge instructions is useful to downstream optimizations. Since VPERM is essentially opaque to all subsequent optimizations, we want to avoid it as much as possible. Other permute instructions have semantics that can be reasoned about much more easily in later optimizations. This patch does the following: - Canonicalize shuffles so that the first element comes from the first vector (since that's what most of the mask matching functions want) - Switch the elements that come from splat vectors so that they match the corresponding elements from the other vector (to allow for merges) - Adds debugging messages for when a shuffle is matched to a VPERM so that anyone interested in improving this further can get the info for their code Differential revision: https://reviews.llvm.org/D77448
275 lines
8.3 KiB
LLVM
275 lines
8.3 KiB
LLVM
; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9LE
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; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9BE
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; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8LE
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; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8BE
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; Function Attrs: norecurse nounwind readonly
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define <2 x i64> @s2v_test1(i64* nocapture readonly %int64, <2 x i64> %vec) {
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; P9LE-LABEL: s2v_test1:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: lfd f0, 0(r3)
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; P9LE-NEXT: xxmrghd v2, v2, vs0
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; P9LE-NEXT: blr
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; P9BE-LABEL: s2v_test1:
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; P9BE: # %bb.0: # %entry
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; P9BE-NEXT: lfd f0, 0(r3)
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; P9BE-NEXT: xxpermdi v2, vs0, v2, 1
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; P9BE-NEXT: blr
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entry:
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%0 = load i64, i64* %int64, align 8
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%vecins = insertelement <2 x i64> %vec, i64 %0, i32 0
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ret <2 x i64> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <2 x i64> @s2v_test2(i64* nocapture readonly %int64, <2 x i64> %vec) {
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; P9LE-LABEL: s2v_test2:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: lfd f0, 8(r3)
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; P9LE-NEXT: xxmrghd v2, v2, vs0
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; P9LE-NEXT: blr
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; P9BE-LABEL: s2v_test2:
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; P9BE: # %bb.0: # %entry
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; P9BE-NEXT: lfd f0, 8(r3)
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; P9BE-NEXT: xxpermdi v2, vs0, v2, 1
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; P9BE-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds i64, i64* %int64, i64 1
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%0 = load i64, i64* %arrayidx, align 8
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%vecins = insertelement <2 x i64> %vec, i64 %0, i32 0
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ret <2 x i64> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <2 x i64> @s2v_test3(i64* nocapture readonly %int64, <2 x i64> %vec, i32 signext %Idx) {
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; P9LE-LABEL: s2v_test3:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: sldi r4, r7, 3
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; P9LE-NEXT: lfdx f0, r3, r4
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; P9LE-NEXT: xxmrghd v2, v2, vs0
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; P9LE-NEXT: blr
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; P9BE-LABEL: s2v_test3
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; P9BE: # %bb.0: # %entry
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; P9BE-NEXT: sldi r4, r7, 3
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; P9BE-NEXT: lfdx f0, r3, r4
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; P9BE-NEXT: xxpermdi v2, vs0, v2, 1
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; P9BE-NEXT: blr
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entry:
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%idxprom = sext i32 %Idx to i64
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%arrayidx = getelementptr inbounds i64, i64* %int64, i64 %idxprom
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%0 = load i64, i64* %arrayidx, align 8
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%vecins = insertelement <2 x i64> %vec, i64 %0, i32 0
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ret <2 x i64> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <2 x i64> @s2v_test4(i64* nocapture readonly %int64, <2 x i64> %vec) {
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; P9LE-LABEL: s2v_test4:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: lfd f0, 8(r3)
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; P9LE-NEXT: xxmrghd v2, v2, vs0
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; P9LE-NEXT: blr
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; P9BE-LABEL: s2v_test4:
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; P9BE: # %bb.0: # %entry
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; P9BE-NEXT: lfd f0, 8(r3)
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; P9BE-NEXT: xxpermdi v2, vs0, v2, 1
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; P9BE-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds i64, i64* %int64, i64 1
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%0 = load i64, i64* %arrayidx, align 8
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%vecins = insertelement <2 x i64> %vec, i64 %0, i32 0
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ret <2 x i64> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <2 x i64> @s2v_test5(<2 x i64> %vec, i64* nocapture readonly %ptr1) {
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; P9LE-LABEL: s2v_test5:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: lfd f0, 0(r5)
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; P9LE-NEXT: xxmrghd v2, v2, vs0
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; P9LE-NEXT: blr
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; P9BE-LABEL: s2v_test5:
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; P9BE: # %bb.0: # %entry
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; P9BE-NEXT: lfd f0, 0(r5)
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; P9BE-NEXT: xxpermdi v2, vs0, v2, 1
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; P9BE-NEXT: blr
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entry:
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%0 = load i64, i64* %ptr1, align 8
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%vecins = insertelement <2 x i64> %vec, i64 %0, i32 0
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ret <2 x i64> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <2 x double> @s2v_test_f1(double* nocapture readonly %f64, <2 x double> %vec) {
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; P9LE-LABEL: s2v_test_f1:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: lfd f0, 0(r3)
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; P9LE-NEXT: xxmrghd v2, v2, vs0
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; P9LE-NEXT: blr
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; P9BE-LABEL: s2v_test_f1:
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; P9BE: # %bb.0: # %entry
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; P9BE-NEXT: lfd f0, 0(r3)
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; P9BE-NEXT: xxpermdi v2, vs0, v2, 1
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; P9BE-NEXT: blr
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; P8LE-LABEL: s2v_test_f1:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: lfdx f0, 0, r3
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; P8LE-NEXT: xxmrghd v2, v2, vs0
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; P8LE-NEXT: blr
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; P8BE-LABEL: s2v_test_f1:
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; P8BE: # %bb.0: # %entry
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; P8BE-NEXT: lfdx f0, 0, r3
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; P8BE-NEXT: xxpermdi v2, vs0, v2, 1
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; P8BE-NEXT: blr
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entry:
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%0 = load double, double* %f64, align 8
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%vecins = insertelement <2 x double> %vec, double %0, i32 0
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ret <2 x double> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <2 x double> @s2v_test_f2(double* nocapture readonly %f64, <2 x double> %vec) {
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; P9LE-LABEL: s2v_test_f2:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: lfd f0, 8(r3)
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; P9LE-NEXT: xxmrghd v2, v2, vs0
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; P9LE-NEXT: blr
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; P9BE-LABEL: s2v_test_f2:
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; P9BE: # %bb.0: # %entry
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; P9BE-NEXT: lfd f0, 8(r3)
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; P9BE-NEXT: xxpermdi v2, vs0, v2, 1
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; P9BE-NEXT: blr
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; P8LE-LABEL: s2v_test_f2:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: lfd f0, 8(r3)
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; P8LE-NEXT: xxmrghd v2, v2, vs0
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; P8LE-NEXT: blr
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; P8BE-LABEL: s2v_test_f2:
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; P8BE: # %bb.0: # %entry
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; P8BE-NEXT: lfd f0, 8(r3)
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; P8BE-NEXT: xxpermdi v2, vs0, v2, 1
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; P8BE-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds double, double* %f64, i64 1
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%0 = load double, double* %arrayidx, align 8
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%vecins = insertelement <2 x double> %vec, double %0, i32 0
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ret <2 x double> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <2 x double> @s2v_test_f3(double* nocapture readonly %f64, <2 x double> %vec, i32 signext %Idx) {
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; P9LE-LABEL: s2v_test_f3:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: sldi r4, r7, 3
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; P9LE-NEXT: lfdx f0, r3, r4
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; P9LE-NEXT: xxmrghd v2, v2, vs0
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; P9LE-NEXT: blr
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; P9BE-LABEL: s2v_test_f3:
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; P9BE: # %bb.0: # %entry
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; P9BE-NEXT: sldi r4, r7, 3
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; P9BE-NEXT: lfdx f0, r3, r4
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; P9BE-NEXT: xxpermdi v2, vs0, v2, 1
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; P9BE-NEXT: blr
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; P8LE-LABEL: s2v_test_f3:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: sldi r4, r7, 3
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; P8LE-NEXT: lfdx f0, r3, r4
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; P8LE-NEXT: xxmrghd v2, v2, vs0
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; P8LE-NEXT: blr
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; P8BE-LABEL: s2v_test_f3:
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; P8BE: # %bb.0: # %entry
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; P8BE-NEXT: sldi r4, r7, 3
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; P8BE-NEXT: lfdx f0, r3, r4
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; P8BE-NEXT: xxpermdi v2, vs0, v2, 1
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; P8BE-NEXT: blr
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entry:
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%idxprom = sext i32 %Idx to i64
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%arrayidx = getelementptr inbounds double, double* %f64, i64 %idxprom
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%0 = load double, double* %arrayidx, align 8
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%vecins = insertelement <2 x double> %vec, double %0, i32 0
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ret <2 x double> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <2 x double> @s2v_test_f4(double* nocapture readonly %f64, <2 x double> %vec) {
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; P9LE-LABEL: s2v_test_f4:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: lfd f0, 8(r3)
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; P9LE-NEXT: xxmrghd v2, v2, vs0
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; P9LE-NEXT: blr
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; P9BE-LABEL: s2v_test_f4:
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; P9BE: # %bb.0: # %entry
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; P9BE-NEXT: lfd f0, 8(r3)
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; P9BE-NEXT: xxpermdi v2, vs0, v2, 1
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; P9BE-NEXT: blr
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; P8LE-LABEL: s2v_test_f4:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: lfd f0, 8(r3)
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; P8LE-NEXT: xxmrghd v2, v2, vs0
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; P8LE-NEXT: blr
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; P8BE-LABEL: s2v_test_f4:
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; P8BE: # %bb.0: # %entry
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; P8BE-NEXT: lfd f0, 8(r3)
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; P8BE-NEXT: xxpermdi v2, vs0, v2, 1
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; P8BE-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds double, double* %f64, i64 1
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%0 = load double, double* %arrayidx, align 8
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%vecins = insertelement <2 x double> %vec, double %0, i32 0
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ret <2 x double> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <2 x double> @s2v_test_f5(<2 x double> %vec, double* nocapture readonly %ptr1) {
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; P9LE-LABEL: s2v_test_f5:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: lfd f0, 0(r5)
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; P9LE-NEXT: xxmrghd v2, v2, vs0
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; P9LE-NEXT: blr
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; P9BE-LABEL: s2v_test_f5:
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; P9BE: # %bb.0: # %entry
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; P9BE-NEXT: lfd f0, 0(r5)
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; P9BE-NEXT: xxpermdi v2, vs0, v2, 1
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; P9BE-NEXT: blr
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; P8LE-LABEL: s2v_test_f5:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: lfdx f0, 0, r5
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; P8LE-NEXT: xxmrghd v2, v2, vs0
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; P8LE-NEXT: blr
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; P8BE-LABEL: s2v_test_f5:
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; P8BE: # %bb.0: # %entry
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; P8BE-NEXT: lfdx f0, 0, r5
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; P8BE-NEXT: xxpermdi v2, vs0, v2, 1
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; P8BE-NEXT: blr
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entry:
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%0 = load double, double* %ptr1, align 8
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%vecins = insertelement <2 x double> %vec, double %0, i32 0
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ret <2 x double> %vecins
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}
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