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845c533554
The attached testcase started failing after the patch to define
isExtractSubvectorCheap with the following pattern mismatch:
ISEL: Starting pattern match
Initial Opcode index to 85068
Match failed at index 85076
LLVM ERROR: Cannot select: t47: v8i16 = insert_subvector undef:v8i16, t43, Constant:i64<0>
The code generated from llvm/lib/Target/AArch64/AArch64InstrInfo.td
def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
(INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
is in ninja/lib/Target/AArch64/AArch64GenDAGISel.inc
At the location of the error it is:
/* 85076*/ OPC_CheckChild2Type, MVT::i32,
And it failed to match the type of operand 2.
Adding another def-pat for i64 fixes the failed def-pat error:
def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i64 0)),
(INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
llvm-svn: 326949
22 lines
824 B
LLVM
22 lines
824 B
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s
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; Check that this does not ICE.
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@d = common dso_local local_unnamed_addr global <4 x i16> zeroinitializer, align 8
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define <8 x i16> @c(i32 %e) {
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entry:
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%0 = load <4 x i16>, <4 x i16>* @d, align 8
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%vminv = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %0)
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%1 = trunc i32 %vminv to i16
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%vecinit3 = insertelement <4 x i16> <i16 undef, i16 undef, i16 0, i16 0>, i16 %1, i32 1
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%call = tail call <8 x i16> @c(i32 0) #3
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%vgetq_lane = extractelement <8 x i16> %call, i32 0
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%vset_lane = insertelement <4 x i16> %vecinit3, i16 %vgetq_lane, i32 0
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%call4 = tail call i32 bitcast (i32 (...)* @k to i32 (<4 x i16>)*)(<4 x i16> %vset_lane) #3
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ret <8 x i16> undef
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}
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declare i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16>)
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declare i32 @k(...)
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