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5f7f2a06d7
I'm not sure what reasons the comment here could have had for not setting these. Without these set, there is an assertion hit during DWARF emission. llvm-svn: 243661
26 lines
727 B
TableGen
26 lines
727 B
TableGen
//===-- AMDGPURegisterInfo.td - AMDGPU register info -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Tablegen register definitions common to all hw codegen targets.
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//
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//===----------------------------------------------------------------------===//
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let Namespace = "AMDGPU" in {
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foreach Index = 0-15 in {
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def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
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}
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def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">;
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}
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include "R600RegisterInfo.td"
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include "SIRegisterInfo.td"
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