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llvm-mirror/test/CodeGen/Hexagon/args.ll
Andrew Trick b4963dd8da VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).
This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling.

Patch by Sergei Larin!

llvm-svn: 149547
2012-02-01 22:13:57 +00:00

19 lines
418 B
LLVM

; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched < %s | FileCheck %s
; CHECK: r[[T0:[0-9]+]] = #7
; CHECK: memw(r29 + #0) = r[[T0]]
; CHECK: r0 = #1
; CHECK: r1 = #2
; CHECK: r2 = #3
; CHECK: r3 = #4
; CHECK: r4 = #5
; CHECK: r5 = #6
define void @foo() nounwind {
entry:
call void @bar(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7)
ret void
}
declare void @bar(i32, i32, i32, i32, i32, i32, i32)