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338 lines
6.4 KiB
TableGen
338 lines
6.4 KiB
TableGen
//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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def HasDSP : Predicate<"Subtarget.hasDSP()">,
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AssemblerPredicate<"FeatureDSP">;
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def HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">,
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AssemblerPredicate<"FeatureDSPR2">;
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// Fields.
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class Field6<bits<6> val> {
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bits<6> V = val;
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}
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def SPECIAL3_OPCODE : Field6<0b011111>;
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def REGIMM_OPCODE : Field6<0b000001>;
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class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
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let Predicates = [HasDSP];
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}
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class PseudoDSP<dag outs, dag ins, list<dag> pattern,
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InstrItinClass itin = IIPseudo>:
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MipsPseudo<outs, ins, pattern, itin> {
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let Predicates = [HasDSP];
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}
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// ADDU.QB sub-class format.
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class ADDU_QB_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010000;
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}
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class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<5> rs;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = 0;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010000;
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}
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// CMPU.EQ.QB sub-class format.
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class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
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bits<5> rs;
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bits<5> rt;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = 0;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010001;
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}
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class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst {
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bits<5> rs;
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bits<5> rt;
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bits<5> rd;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010001;
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}
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class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
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bits<5> rs;
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bits<5> rt;
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bits<5> sa;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = sa;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010001;
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}
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// ABSQ_S.PH sub-class format.
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class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<5> rt;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = 0;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010010;
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}
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class REPL_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<10> imm;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-16} = imm;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010010;
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}
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// SHLL.QB sub-class format.
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class SHLL_QB_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<5> rt;
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bits<5> rs_sa;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs_sa;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010011;
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}
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// LX sub-class format.
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class LX_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<5> base;
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bits<5> index;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = base;
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let Inst{20-16} = index;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b001010;
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}
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// ADDUH.QB sub-class format.
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class ADDUH_QB_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b011000;
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}
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// APPEND sub-class format.
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class APPEND_FMT<bits<5> op> : DSPInst {
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bits<5> rt;
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bits<5> rs;
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bits<5> sa;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = sa;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b110001;
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}
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// DPA.W.PH sub-class format.
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class DPA_W_PH_FMT<bits<5> op> : DSPInst {
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bits<2> ac;
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bits<5> rs;
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bits<5> rt;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-13} = 0;
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let Inst{12-11} = ac;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b110000;
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}
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// MULT sub-class format.
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class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst {
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bits<2> ac;
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bits<5> rs;
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bits<5> rt;
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let Opcode = opcode;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-13} = 0;
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let Inst{12-11} = ac;
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let Inst{10-6} = 0;
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let Inst{5-0} = funct;
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}
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// MFHI sub-class format.
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class MFHI_FMT<bits<6> funct> : DSPInst {
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bits<5> rd;
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bits<2> ac;
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let Inst{31-26} = 0;
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let Inst{25-23} = 0;
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let Inst{22-21} = ac;
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let Inst{20-16} = 0;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0;
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let Inst{5-0} = funct;
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}
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// MTHI sub-class format.
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class MTHI_FMT<bits<6> funct> : DSPInst {
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bits<5> rs;
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bits<2> ac;
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let Inst{31-26} = 0;
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let Inst{25-21} = rs;
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let Inst{20-13} = 0;
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let Inst{12-11} = ac;
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let Inst{10-6} = 0;
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let Inst{5-0} = funct;
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}
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// EXTR.W sub-class format (type 1).
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class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
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bits<5> rt;
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bits<2> ac;
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bits<5> shift_rs;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = shift_rs;
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let Inst{20-16} = rt;
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let Inst{15-13} = 0;
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let Inst{12-11} = ac;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b111000;
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}
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// SHILO sub-class format.
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class SHILO_R1_FMT<bits<5> op> : DSPInst {
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bits<2> ac;
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bits<6> shift;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-20} = shift;
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let Inst{19-13} = 0;
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let Inst{12-11} = ac;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b111000;
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}
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class SHILO_R2_FMT<bits<5> op> : DSPInst {
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bits<2> ac;
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bits<5> rs;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-13} = 0;
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let Inst{12-11} = ac;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b111000;
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}
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class RDDSP_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<10> mask;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-16} = mask;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b111000;
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}
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class WRDSP_FMT<bits<5> op> : DSPInst {
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bits<5> rs;
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bits<10> mask;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-11} = mask;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b111000;
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}
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class BPOSGE32_FMT<bits<5> op> : DSPInst {
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bits<16> offset;
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let Opcode = REGIMM_OPCODE.V;
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let Inst{25-21} = 0;
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let Inst{20-16} = op;
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let Inst{15-0} = offset;
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}
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// INSV sub-class format.
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class INSV_FMT<bits<6> op> : DSPInst {
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bits<5> rt;
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bits<5> rs;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-6} = 0;
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let Inst{5-0} = op;
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}
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