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https://github.com/RPCS3/llvm-mirror.git
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844 lines
31 KiB
C++
844 lines
31 KiB
C++
//===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SystemZTargetLowering class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "systemz-lower"
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#include "SystemZISelLowering.h"
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#include "SystemZ.h"
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#include "SystemZTargetMachine.h"
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#include "SystemZSubtarget.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CallingConv.h"
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#include "llvm/GlobalVariable.h"
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#include "llvm/GlobalAlias.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/VectorExtras.h"
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using namespace llvm;
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SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
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TargetLowering(tm, new TargetLoweringObjectFileELF()),
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Subtarget(*tm.getSubtargetImpl()), TM(tm) {
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RegInfo = TM.getRegisterInfo();
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// Set up the register classes.
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addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
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addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
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addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
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addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
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if (!UseSoftFloat) {
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addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
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addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
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addLegalFPImmediate(APFloat(+0.0)); // lzer
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addLegalFPImmediate(APFloat(+0.0f)); // lzdr
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addLegalFPImmediate(APFloat(-0.0)); // lzer + lner
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addLegalFPImmediate(APFloat(-0.0f)); // lzdr + lndr
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}
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// Compute derived properties from the register classes
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computeRegisterProperties();
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// Set shifts properties
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setShiftAmountType(MVT::i64);
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// Provide all sorts of operation actions
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
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setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
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setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
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setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
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setStackPointerRegisterToSaveRestore(SystemZ::R15D);
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setSchedulingPreference(SchedulingForLatency);
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setBooleanContents(ZeroOrOneBooleanContent);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::i32, Custom);
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setOperationAction(ISD::BR_CC, MVT::i64, Custom);
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setOperationAction(ISD::BR_CC, MVT::f32, Custom);
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setOperationAction(ISD::BR_CC, MVT::f64, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::JumpTable, MVT::i64, Custom);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
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setOperationAction(ISD::SDIV, MVT::i32, Expand);
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setOperationAction(ISD::UDIV, MVT::i32, Expand);
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setOperationAction(ISD::SDIV, MVT::i64, Expand);
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setOperationAction(ISD::UDIV, MVT::i64, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i64, Expand);
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setOperationAction(ISD::UREM, MVT::i64, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTPOP, MVT::i64, Expand);
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setOperationAction(ISD::CTTZ, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::i64, Expand);
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setOperationAction(ISD::CTLZ, MVT::i32, Promote);
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setOperationAction(ISD::CTLZ, MVT::i64, Legal);
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// FIXME: Can we lower these 2 efficiently?
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setOperationAction(ISD::SETCC, MVT::i32, Expand);
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setOperationAction(ISD::SETCC, MVT::i64, Expand);
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setOperationAction(ISD::SETCC, MVT::f32, Expand);
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setOperationAction(ISD::SETCC, MVT::f64, Expand);
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SELECT, MVT::i64, Expand);
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setOperationAction(ISD::SELECT, MVT::f32, Expand);
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setOperationAction(ISD::SELECT, MVT::f64, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
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setOperationAction(ISD::MULHS, MVT::i64, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
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// FIXME: Can we support these natively?
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setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
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// Lower some FP stuff
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setOperationAction(ISD::FSIN, MVT::f32, Expand);
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setOperationAction(ISD::FSIN, MVT::f64, Expand);
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setOperationAction(ISD::FCOS, MVT::f32, Expand);
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setOperationAction(ISD::FCOS, MVT::f64, Expand);
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setOperationAction(ISD::FREM, MVT::f32, Expand);
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setOperationAction(ISD::FREM, MVT::f64, Expand);
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// We have only 64-bit bitconverts
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setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
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setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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}
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SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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case ISD::BR_CC: return LowerBR_CC(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
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case ISD::JumpTable: return LowerJumpTable(Op, DAG);
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case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
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default:
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llvm_unreachable("Should not custom lower this!");
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return SDValue();
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}
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}
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//===----------------------------------------------------------------------===//
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// SystemZ Inline Assembly Support
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//===----------------------------------------------------------------------===//
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/// getConstraintType - Given a constraint letter, return the type of
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/// constraint it is for this target.
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TargetLowering::ConstraintType
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SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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case 'r':
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return C_RegisterClass;
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default:
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break;
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}
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}
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return TargetLowering::getConstraintType(Constraint);
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}
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std::pair<unsigned, const TargetRegisterClass*>
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SystemZTargetLowering::
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getRegForInlineAsmConstraint(const std::string &Constraint,
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EVT VT) const {
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if (Constraint.size() == 1) {
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// GCC Constraint Letters
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switch (Constraint[0]) {
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default: break;
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case 'r': // GENERAL_REGS
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if (VT == MVT::i32)
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return std::make_pair(0U, SystemZ::GR32RegisterClass);
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else if (VT == MVT::i128)
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return std::make_pair(0U, SystemZ::GR128RegisterClass);
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return std::make_pair(0U, SystemZ::GR64RegisterClass);
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}
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}
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return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
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}
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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#include "SystemZGenCallingConv.inc"
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SDValue
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SystemZTargetLowering::LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg>
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&Ins,
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DebugLoc dl,
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SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) {
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switch (CallConv) {
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default:
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llvm_unreachable("Unsupported calling convention");
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case CallingConv::C:
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case CallingConv::Fast:
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return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
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}
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}
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SDValue
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SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg,
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bool isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) {
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switch (CallConv) {
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default:
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llvm_unreachable("Unsupported calling convention");
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case CallingConv::Fast:
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case CallingConv::C:
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return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
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Outs, Ins, dl, DAG, InVals);
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}
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}
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/// LowerCCCArguments - transform physical registers into virtual registers and
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/// generate load operations for arguments places on the stack.
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// FIXME: struct return stuff
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// FIXME: varargs
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SDValue
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SystemZTargetLowering::LowerCCCArguments(SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg>
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&Ins,
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DebugLoc dl,
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SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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// Assign locations to all of the incoming arguments.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
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ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
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if (isVarArg)
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llvm_report_error("Varargs not supported yet");
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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SDValue ArgValue;
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CCValAssign &VA = ArgLocs[i];
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EVT LocVT = VA.getLocVT();
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if (VA.isRegLoc()) {
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// Arguments passed in registers
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TargetRegisterClass *RC;
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switch (LocVT.getSimpleVT().SimpleTy) {
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default:
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#ifndef NDEBUG
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errs() << "LowerFormalArguments Unhandled argument type: "
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<< LocVT.getSimpleVT().SimpleTy
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<< "\n";
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#endif
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llvm_unreachable(0);
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case MVT::i64:
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RC = SystemZ::GR64RegisterClass;
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break;
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case MVT::f32:
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RC = SystemZ::FP32RegisterClass;
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break;
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case MVT::f64:
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RC = SystemZ::FP64RegisterClass;
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break;
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}
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unsigned VReg = RegInfo.createVirtualRegister(RC);
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RegInfo.addLiveIn(VA.getLocReg(), VReg);
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ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
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} else {
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// Sanity check
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assert(VA.isMemLoc());
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// Create the nodes corresponding to a load from this parameter slot.
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8,
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VA.getLocMemOffset());
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// Create the SelectionDAG nodes corresponding to a load
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// from this parameter
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SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
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ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN,
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PseudoSourceValue::getFixedStack(FI), 0);
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}
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// If this is an 8/16/32-bit value, it is really passed promoted to 64
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// bits. Insert an assert[sz]ext to capture this, then truncate to the
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// right size.
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if (VA.getLocInfo() == CCValAssign::SExt)
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ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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if (VA.getLocInfo() != CCValAssign::Full)
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ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
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InVals.push_back(ArgValue);
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}
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return Chain;
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}
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/// LowerCCCCallTo - functions arguments are copied from virtual regs to
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/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
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/// TODO: sret.
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SDValue
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SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg,
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bool isTailCall,
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const SmallVectorImpl<ISD::OutputArg>
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&Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) {
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MachineFunction &MF = DAG.getMachineFunction();
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// Offset to first argument stack slot.
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const unsigned FirstArgOffset = 160;
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
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ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
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getPointerTy(), true));
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SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
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SmallVector<SDValue, 12> MemOpChains;
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SDValue StackPtr;
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// Walk the register/memloc assignments, inserting copies/loads.
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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SDValue Arg = Outs[i].Val;
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// Promote the value if needed.
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switch (VA.getLocInfo()) {
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default: assert(0 && "Unknown loc info!");
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case CCValAssign::Full: break;
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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case CCValAssign::ZExt:
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Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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case CCValAssign::AExt:
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Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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}
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// Arguments that can be passed on register must be kept at RegsToPass
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// vector
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if (VA.isRegLoc()) {
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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} else {
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assert(VA.isMemLoc());
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if (StackPtr.getNode() == 0)
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StackPtr =
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DAG.getCopyFromReg(Chain, dl,
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(RegInfo->hasFP(MF) ?
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SystemZ::R11D : SystemZ::R15D),
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getPointerTy());
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unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
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SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
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StackPtr,
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DAG.getIntPtrConstant(Offset));
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MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
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PseudoSourceValue::getStack(), Offset));
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}
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}
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// Transform all store nodes into one single node because all store nodes are
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// independent of each other.
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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// Build a sequence of copy-to-reg nodes chained together with token chain and
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// flag operands which copy the outgoing args into registers. The InFlag in
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// necessary since all emited instructions must be stuck together.
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SDValue InFlag;
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
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Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
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RegsToPass[i].second, InFlag);
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InFlag = Chain.getValue(1);
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}
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// If the callee is a GlobalAddress node (quite common, every direct call is)
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// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
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// Likewise ExternalSymbol -> TargetExternalSymbol.
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
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else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
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Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
|
|
|
|
// Returns a chain & a flag for retval copy to use.
|
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
|
|
SmallVector<SDValue, 8> Ops;
|
|
Ops.push_back(Chain);
|
|
Ops.push_back(Callee);
|
|
|
|
// Add argument registers to the end of the list so that they are
|
|
// known live into the call.
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
|
|
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
|
|
RegsToPass[i].second.getValueType()));
|
|
|
|
if (InFlag.getNode())
|
|
Ops.push_back(InFlag);
|
|
|
|
Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
|
|
InFlag = Chain.getValue(1);
|
|
|
|
// Create the CALLSEQ_END node.
|
|
Chain = DAG.getCALLSEQ_END(Chain,
|
|
DAG.getConstant(NumBytes, getPointerTy(), true),
|
|
DAG.getConstant(0, getPointerTy(), true),
|
|
InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
// Handle result values, copying them out of physregs into vregs that we
|
|
// return.
|
|
return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
|
|
DAG, InVals);
|
|
}
|
|
|
|
/// LowerCallResult - Lower the result values of a call into the
|
|
/// appropriate copies out of appropriate physical registers.
|
|
///
|
|
SDValue
|
|
SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg>
|
|
&Ins,
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) {
|
|
|
|
// Assign locations to each value returned by this call.
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
|
|
*DAG.getContext());
|
|
|
|
CCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
|
|
|
|
// Copy all of the result registers out of their specified physreg.
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
CCValAssign &VA = RVLocs[i];
|
|
|
|
Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
|
|
VA.getLocVT(), InFlag).getValue(1);
|
|
SDValue RetValue = Chain.getValue(0);
|
|
InFlag = Chain.getValue(2);
|
|
|
|
// If this is an 8/16/32-bit value, it is really passed promoted to 64
|
|
// bits. Insert an assert[sz]ext to capture this, then truncate to the
|
|
// right size.
|
|
if (VA.getLocInfo() == CCValAssign::SExt)
|
|
RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
|
|
DAG.getValueType(VA.getValVT()));
|
|
else if (VA.getLocInfo() == CCValAssign::ZExt)
|
|
RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
|
|
DAG.getValueType(VA.getValVT()));
|
|
|
|
if (VA.getLocInfo() != CCValAssign::Full)
|
|
RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
|
|
|
|
InVals.push_back(RetValue);
|
|
}
|
|
|
|
return Chain;
|
|
}
|
|
|
|
|
|
SDValue
|
|
SystemZTargetLowering::LowerReturn(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
DebugLoc dl, SelectionDAG &DAG) {
|
|
|
|
// CCValAssign - represent the assignment of the return value to a location
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
|
|
// CCState - Info about the registers and stack slot.
|
|
CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
|
|
RVLocs, *DAG.getContext());
|
|
|
|
// Analize return values.
|
|
CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
|
|
|
|
// If this is the first return lowered for this function, add the regs to the
|
|
// liveout set for the function.
|
|
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i)
|
|
if (RVLocs[i].isRegLoc())
|
|
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
|
|
}
|
|
|
|
SDValue Flag;
|
|
|
|
// Copy the result values into the output registers.
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
CCValAssign &VA = RVLocs[i];
|
|
SDValue ResValue = Outs[i].Val;
|
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
|
|
|
// If this is an 8/16/32-bit value, it is really should be passed promoted
|
|
// to 64 bits.
|
|
if (VA.getLocInfo() == CCValAssign::SExt)
|
|
ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
|
|
else if (VA.getLocInfo() == CCValAssign::ZExt)
|
|
ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
|
|
else if (VA.getLocInfo() == CCValAssign::AExt)
|
|
ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
|
|
|
|
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
|
|
|
|
// Guarantee that all emitted copies are stuck together,
|
|
// avoiding something bad.
|
|
Flag = Chain.getValue(1);
|
|
}
|
|
|
|
if (Flag.getNode())
|
|
return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
|
|
|
|
// Return Void
|
|
return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
|
|
ISD::CondCode CC, SDValue &SystemZCC,
|
|
SelectionDAG &DAG) {
|
|
// FIXME: Emit a test if RHS is zero
|
|
|
|
bool isUnsigned = false;
|
|
SystemZCC::CondCodes TCC;
|
|
switch (CC) {
|
|
default:
|
|
llvm_unreachable("Invalid integer condition!");
|
|
case ISD::SETEQ:
|
|
case ISD::SETOEQ:
|
|
TCC = SystemZCC::E;
|
|
break;
|
|
case ISD::SETUEQ:
|
|
TCC = SystemZCC::NLH;
|
|
break;
|
|
case ISD::SETNE:
|
|
case ISD::SETONE:
|
|
TCC = SystemZCC::NE;
|
|
break;
|
|
case ISD::SETUNE:
|
|
TCC = SystemZCC::LH;
|
|
break;
|
|
case ISD::SETO:
|
|
TCC = SystemZCC::O;
|
|
break;
|
|
case ISD::SETUO:
|
|
TCC = SystemZCC::NO;
|
|
break;
|
|
case ISD::SETULE:
|
|
if (LHS.getValueType().isFloatingPoint()) {
|
|
TCC = SystemZCC::NH;
|
|
break;
|
|
}
|
|
isUnsigned = true; // FALLTHROUGH
|
|
case ISD::SETLE:
|
|
case ISD::SETOLE:
|
|
TCC = SystemZCC::LE;
|
|
break;
|
|
case ISD::SETUGE:
|
|
if (LHS.getValueType().isFloatingPoint()) {
|
|
TCC = SystemZCC::NL;
|
|
break;
|
|
}
|
|
isUnsigned = true; // FALLTHROUGH
|
|
case ISD::SETGE:
|
|
case ISD::SETOGE:
|
|
TCC = SystemZCC::HE;
|
|
break;
|
|
case ISD::SETUGT:
|
|
if (LHS.getValueType().isFloatingPoint()) {
|
|
TCC = SystemZCC::NLE;
|
|
break;
|
|
}
|
|
isUnsigned = true; // FALLTHROUGH
|
|
case ISD::SETGT:
|
|
case ISD::SETOGT:
|
|
TCC = SystemZCC::H;
|
|
break;
|
|
case ISD::SETULT:
|
|
if (LHS.getValueType().isFloatingPoint()) {
|
|
TCC = SystemZCC::NHE;
|
|
break;
|
|
}
|
|
isUnsigned = true; // FALLTHROUGH
|
|
case ISD::SETLT:
|
|
case ISD::SETOLT:
|
|
TCC = SystemZCC::L;
|
|
break;
|
|
}
|
|
|
|
SystemZCC = DAG.getConstant(TCC, MVT::i32);
|
|
|
|
DebugLoc dl = LHS.getDebugLoc();
|
|
return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
|
|
dl, MVT::Flag, LHS, RHS);
|
|
}
|
|
|
|
|
|
SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
|
|
SDValue Chain = Op.getOperand(0);
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
|
|
SDValue LHS = Op.getOperand(2);
|
|
SDValue RHS = Op.getOperand(3);
|
|
SDValue Dest = Op.getOperand(4);
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
SDValue SystemZCC;
|
|
SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
|
|
return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
|
|
Chain, Dest, SystemZCC, Flag);
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
|
|
SDValue LHS = Op.getOperand(0);
|
|
SDValue RHS = Op.getOperand(1);
|
|
SDValue TrueV = Op.getOperand(2);
|
|
SDValue FalseV = Op.getOperand(3);
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
SDValue SystemZCC;
|
|
SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
|
|
|
|
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
|
|
SmallVector<SDValue, 4> Ops;
|
|
Ops.push_back(TrueV);
|
|
Ops.push_back(FalseV);
|
|
Ops.push_back(SystemZCC);
|
|
Ops.push_back(Flag);
|
|
|
|
return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
|
|
}
|
|
|
|
SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
|
|
SelectionDAG &DAG) {
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
|
int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
|
|
|
|
bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
|
|
bool ExtraLoadRequired =
|
|
Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false);
|
|
|
|
SDValue Result;
|
|
if (!IsPic && !ExtraLoadRequired) {
|
|
Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
|
|
Offset = 0;
|
|
} else {
|
|
unsigned char OpFlags = 0;
|
|
if (ExtraLoadRequired)
|
|
OpFlags = SystemZII::MO_GOTENT;
|
|
|
|
Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
|
|
}
|
|
|
|
Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
|
|
getPointerTy(), Result);
|
|
|
|
if (ExtraLoadRequired)
|
|
Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
|
|
PseudoSourceValue::getGOT(), 0);
|
|
|
|
// If there was a non-zero offset that we didn't fold, create an explicit
|
|
// addition for it.
|
|
if (Offset != 0)
|
|
Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
|
|
DAG.getConstant(Offset, getPointerTy()));
|
|
|
|
return Result;
|
|
}
|
|
|
|
// FIXME: PIC here
|
|
SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
|
|
SelectionDAG &DAG) {
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
|
|
SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
|
|
|
|
return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
|
|
}
|
|
|
|
|
|
// FIXME: PIC here
|
|
// FIXME: This is just dirty hack. We need to lower cpool properly
|
|
SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op,
|
|
SelectionDAG &DAG) {
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
|
|
|
|
SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
|
|
CP->getAlignment(),
|
|
CP->getOffset());
|
|
|
|
return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
|
|
}
|
|
|
|
const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|
switch (Opcode) {
|
|
case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
|
|
case SystemZISD::CALL: return "SystemZISD::CALL";
|
|
case SystemZISD::BRCOND: return "SystemZISD::BRCOND";
|
|
case SystemZISD::CMP: return "SystemZISD::CMP";
|
|
case SystemZISD::UCMP: return "SystemZISD::UCMP";
|
|
case SystemZISD::SELECT: return "SystemZISD::SELECT";
|
|
case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper";
|
|
default: return NULL;
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Other Lowering Code
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
MachineBasicBlock*
|
|
SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
MachineBasicBlock *BB,
|
|
DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
|
|
const SystemZInstrInfo &TII = *TM.getInstrInfo();
|
|
DebugLoc dl = MI->getDebugLoc();
|
|
assert((MI->getOpcode() == SystemZ::Select32 ||
|
|
MI->getOpcode() == SystemZ::SelectF32 ||
|
|
MI->getOpcode() == SystemZ::Select64 ||
|
|
MI->getOpcode() == SystemZ::SelectF64) &&
|
|
"Unexpected instr type to insert");
|
|
|
|
// To "insert" a SELECT instruction, we actually have to insert the diamond
|
|
// control-flow pattern. The incoming instruction knows the destination vreg
|
|
// to set, the condition code register to branch on, the true/false values to
|
|
// select between, and a branch opcode to use.
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
MachineFunction::iterator I = BB;
|
|
++I;
|
|
|
|
// thisMBB:
|
|
// ...
|
|
// TrueVal = ...
|
|
// cmpTY ccX, r1, r2
|
|
// jCC copy1MBB
|
|
// fallthrough --> copy0MBB
|
|
MachineBasicBlock *thisMBB = BB;
|
|
MachineFunction *F = BB->getParent();
|
|
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
|
|
BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
|
|
F->insert(I, copy0MBB);
|
|
F->insert(I, copy1MBB);
|
|
// Inform sdisel of the edge changes.
|
|
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
|
|
SE = BB->succ_end(); SI != SE; ++SI)
|
|
EM->insert(std::make_pair(*SI, copy1MBB));
|
|
// Update machine-CFG edges by transferring all successors of the current
|
|
// block to the new block which will contain the Phi node for the select.
|
|
copy1MBB->transferSuccessors(BB);
|
|
// Next, add the true and fallthrough blocks as its successors.
|
|
BB->addSuccessor(copy0MBB);
|
|
BB->addSuccessor(copy1MBB);
|
|
|
|
// copy0MBB:
|
|
// %FalseValue = ...
|
|
// # fallthrough to copy1MBB
|
|
BB = copy0MBB;
|
|
|
|
// Update machine-CFG edges
|
|
BB->addSuccessor(copy1MBB);
|
|
|
|
// copy1MBB:
|
|
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
|
// ...
|
|
BB = copy1MBB;
|
|
BuildMI(BB, dl, TII.get(SystemZ::PHI),
|
|
MI->getOperand(0).getReg())
|
|
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
|
|
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
|
|
|
|
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
|
return BB;
|
|
}
|