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182b0cd903
llvm-mirror/lib/MCA
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Andrew Savonichev 182b0cd903 [MCA] Disable RCU for InOrderIssueStage 
This is a follow-up for:
D98604 [MCA] Ensure that writes occur in-order

When instructions are aligned by the order of writes, they retire
in-order naturally. There is no need for an RCU, so it is disabled.

Differential Revision: https://reviews.llvm.org/D98628
2021-03-24 13:54:04 +03:00
..
HardwareUnits [MCA] Disable RCU for InOrderIssueStage 2021-03-24 13:54:04 +03:00
Stages [MCA] Disable RCU for InOrderIssueStage 2021-03-24 13:54:04 +03:00
CMakeLists.txt [MCA] Add support for in-order CPUs 2021-03-04 14:08:19 +03:00
CodeEmitter.cpp [MC][Bugfix] Remove redundant parameter for relaxInstruction 2020-04-21 11:06:55 +08:00
Context.cpp [MCA] Disable RCU for InOrderIssueStage 2021-03-24 13:54:04 +03:00
HWEventListener.cpp
InstrBuilder.cpp [MCA] Add support for in-order CPUs 2021-03-04 14:08:19 +03:00
Instruction.cpp [MCA] Improved handling of negative read-advance cycles. 2021-03-23 14:47:23 +00:00
Pipeline.cpp Revert "Remove redundant "std::move"s in return statements" 2020-02-10 07:07:40 -08:00
Support.cpp [MCA] Improved debug prints. NFC 2019-02-12 16:18:57 +00:00