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a147209ed5
This needed two fixes:
* 32-bit instructions were read in the wrong order. The machine code
swaps the two 16-bit instruction words, which wasn't undone when
decoding instructions.
* Jump and call instructions don't encode the lowest address bit,
which is always zero. Therefore, the address needed to be shifted by
one to fix that.
Differential Revision: https://reviews.llvm.org/D81961
26 lines
915 B
ArmAsm
26 lines
915 B
ArmAsm
; RUN: llvm-mc -triple avr -mattr=sram -show-encoding < %s | FileCheck %s
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; RUN: llvm-mc -filetype=obj -triple avr -mattr=sram < %s | llvm-objdump -dr --mattr=sram - | FileCheck -check-prefix=CHECK-INST %s
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foo:
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lds r16, 241
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lds r29, 190
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lds r22, 172
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lds r27, 92
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lds r4, SYMBOL+12
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; CHECK: lds r16, 241 ; encoding: [0x00,0x91,0xf1,0x00]
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; CHECK: lds r29, 190 ; encoding: [0xd0,0x91,0xbe,0x00]
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; CHECK: lds r22, 172 ; encoding: [0x60,0x91,0xac,0x00]
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; CHECK: lds r27, 92 ; encoding: [0xb0,0x91,0x5c,0x00]
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; CHECK: lds r4, SYMBOL+12 ; encoding: [0x40,0x90,A,A]
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; CHECK: ; fixup A - offset: 2, value: SYMBOL+12, kind: fixup_16
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; CHECK-INST: lds r16, 241
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; CHECK-INST: lds r29, 190
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; CHECK-INST: lds r22, 172
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; CHECK-INST: lds r27, 92
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; CHECK-INST: lds r4, 0
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; CHECK-INST: R_AVR_16 SYMBOL+0xc
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